PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 201

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Table 51
Register Setting
IMR0.RME = 0
IMR0.RPF = 0
IMR1.XPR = 0
IMR4.RME2=0
IMR4.RPF2=0
IMR5.XPR2=0
IMR5.RME3=0
IMR5.RPF3=0
IMR5.XPR3=0
RTR3.TS16 = 1
TTR3.TS16 = 1
TSEO = 00
TSBS1 = FF
TSBS2= FF
TSBS3= FF
TSS2= 01
TSS3= 02
Table 52
Register Setting
XSP.CASEN = 1
CCR1.EITS = 0
IMR0.CASC = 0
Note: After the device initialization a software reset should be executed by setting
6.4
The FALC
according to ITU-T G.703, chapter 13. The configuration for this mode is
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•
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•
User’s Manual
Hardware Description
2.048 MHz input clock on RL1/RL2
2.048 MHz output clock on XL1/XL2
Transmit clock referenced by SCLKX (CMR1.DXSS = 0)
Transmit pulse mask set to XMP0 = FF
of bits CMDR.XRES/RRES.
H
H
®
H
Digital Clock Interface Mode
56 can be used to receive and transmit clock information instead of data
H
H
H
HDLC Controller Initialization (E1) (cont’d)
CAS-CC Initialization (E1)
Function
Unmask interrupts for HDLC processor requests.
Select TS16 for HDLC data reception and transmission.
Even and odd frames are used for HDLC reception and
transmission.
Select all bits of selected time slot (channel 1).
Select all bits of selected time slot (channel 2).
Select all bits of selected time slot (channel 3).
Select time slot 1 for HDLC channel 2.
Select time slot 2 for HDLC channel 3.
Function
Send CAS info stored in the XS(16:1) registers.
Enable interrupt with any data change in the RS(16:1) registers.
201
H
, XPM1 = BD
H
Operational Description E1
, and XPM2 = 07
DS1.1, 2003-10-23
PEF 2256 H/E
H
FALC
®
56