PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 268

no-image

PEF2256

Manufacturer Part Number
PEF2256
Description
E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
Manufacturer
INFINEON [Infineon Technologies AG]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PEF2256EV2.1ES
Manufacturer:
HARRIS
Quantity:
101
Part Number:
PEF2256EV2.2
Manufacturer:
INFINEON
Quantity:
513
Part Number:
PEF2256EV2.2
Manufacturer:
LANTIQ
Quantity:
8 000
Part Number:
PEF2256H
Manufacturer:
infineon
Quantity:
6
Part Number:
PEF2256H V1.2
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
Part Number:
PEF2256HV
Manufacturer:
INF
Quantity:
20 000
Part Number:
PEF2256HV2.1
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
Company:
Part Number:
PEF2256HV2.1
Quantity:
116
Part Number:
PEF2256HV2.2
Manufacturer:
INFINEON
Quantity:
672
Part Number:
PEF2256HV2.2
Manufacturer:
INFINEON
Quantity:
8 000
Part Number:
PEF2256HV2.2
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
Company:
Part Number:
PEF2256HV2.2
Quantity:
7
RESX
RESR
TTRF
DAF
User’s Manual
Hardware Description
Rising Edge Synchronous Pulse Transmit
Depending on this bit all transmit system interface data and marker
are clocked or sampled with the selected active edge.
CMR2.IXSC = 0:
0
1
CMR2.IXSC = 1:
The value of RESX bit has no impact on the selected edge of the PCM
highway clock but value of RESR bit is used as RESX.
Example: If RESR = 0, the rising edge of PCM highway clock is the
selected one for sampling data on XDI and vice versa.
Rising Edge Synchronous Pulse Receive
Depending on this bit all receive system interface data and marker are
clocked with the selected active edge.
0 =
1 =
Note: If bit CMR2.IRSP is set, the behavior of signal RFM (if used) is
TTR Register Function (Fractional E1 Access)
Setting this bit the function of the TTR(4:1) registers is changed. A
one in each TTR register forces the XSIGM marker high for the
corresponding time slot and controls sampling of the time slots
provided on pin XSIG. XSIG is selected by PC(4:1).XPC(3:0).
Disable Automatic Freeze
0 =
1 =
latched with the first falling edge of the selected PCM highway
clock.
latched with the first rising edge of the selected PCM highway
clock.
Latched with the first falling edge of the selected PCM highway
clock.
Latched with the first rising edge of the selected PCM highway
clock.
inverse (1 = falling edge, 0 = rising edge)
Signaling is automatically frozen if one of the following alarms
occurred: Loss-Of-Signal (FRS0.LOS), Loss of CAS Frame
Alignment (FRS1.TS16LFA), or receive slips (ISR3.RSP/N).
Automatic freezing of signaling data is disabled. Updating of the
signaling buffer is also done if one of the above described alarm
conditions is active. However, updating of the signaling buffer
is stopped if SIC2.FFS is set. Significant only if the serial
signaling access is enabled.
268
DS1.1, 2003-10-23
PEF 2256 H/E
E1 Registers
FALC
®
56

Related parts for PEF2256