PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 329

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Interrupt Status Register 3 (Read)
ISR3
All bits are reset when ISR3 is read.
If bit GCR.VIS is set, interrupt statuses in ISR3 are flagged although they are masked by
register IMR3. However, these masked interrupt statuses neither generate a signal on
INT, nor are visible in register GIS.
ES
SEC
LMFA16
AIS16
User’s Manual
Hardware Description
ES
7
Errored Second
This bit is set if at least one enabled interrupt source by ESM is set
during the time interval of one second. Interrupt sources of ESM
register:
LFA = Loss of frame alignment detected (FRS0.LFA)
FER = Framing error received
CER = CRC error received
AIS
LOS = Loss-of-signal (FRS0.LOS)
CVE = Code violation detected
SLIP = Receive Slip positive/negative detected
EBE = E-Bit error detected (RSP.RS13/15)
Second Timer
The internal one-second timer has expired. The timer is derived from
clock RCLK or external pin SEC/FSC.
Loss of Multiframe Alignment TS 16
Multiframe alignment of time slot 16 has been lost if two consecutive
multiframe pattern are not detected or if in 16 consecutive time slot 16
all bits are reset.
If register GCR.SCI is high this interrupt status bit is set with every
change of state of FRS1.TS16LFA.
Alarm Indication Signal TS 16 Status Change
The alarm indication signal AIS in time slot 16 for the 64-kbit/s
channel associated signaling is detected or cleared. A change in bit
FRS1.TS16AIS sets this interrupt. (This bit is set if the incoming TS
16 signal contains less than 4 zeros in each of two consecutive TS16-
multiframe periods.)
SEC
= Alarm indication signal (FRS0.AIS)
LMFA16
AIS16
329
RA16
RSN
DS1.1, 2003-10-23
PEF 2256 H/E
RSP
E1 Registers
0
FALC
(6B)
®
56