PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 409

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

XHF2
XTF2
XME2
SRES2
Command Register 4 (Write)
Value after reset: 00
CMDR4
RMC3
XREP3
User’s Manual
Hardware Description
RMC3
7
Transmit HDLC Frame - HDLC Channel 2
After having written up to 32 bytes to the XFIFO2, this command
initiates the transmission of a HDLC frame.
Transmit Transparent Frame - HDLC Channel 2
Initiates the transmission of a transparent frame without HDLC
framing.
Transmit Message End - HDLC Channel 2
Indicates that the data block written last to the XFIFO2 completes the
current frame. The FALC
properly by appending the CRC and the closing flag sequence to the
data.
Signaling Transmitter Reset - HDLC Channel 2
The transmitter of the signaling controller is reset. XFIFO2 is cleared
of any data and an abort sequence (seven 1s) followed by interframe
time fill is transmitted. In response to SRES2 an XPR2 interrupt is
generated.
This command can be used by the CPU to abort a frame currently in
transmission.
Receive Message Complete - HDLC Channel 3
Confirmation from CPU to FALC
has been fetched following an RPF3 or RME3 interrupt, thus the
occupied space in the RFIFO3 can be released.
Transmission Repeat - HDLC Channel 3
If XREP3 is set together with XTF3 (write 24H to CMDR4), the FALC
repeatedly transmits the contents of the XFIFO3 (1 to 32 bytes)
without HDLC framing fully transparently, i.e. without flag, CRC.
The cyclic transmission is stopped with an SRES3 command or by
resetting XREP3.
H
XREP3
409
®
XHF3
can terminate the transmission operation
®
that the current frame or data block
XTF3
XME3
DS1.1, 2003-10-23
T1/J1 Registers
SRES3
PEF 2256 H/E
0
FALC
(89)
®
56
®