PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 254
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PEF2256
Manufacturer Part Number
PEF2256
Description
E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
Manufacturer
INFINEON [Infineon Technologies AG]
Datasheet
1.PEF2256.pdf
(518 pages)
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Transmit S
Value after reset: 00
XSA4
XSA5
XSA6
XSA7
XSA8
XSA(8:4)
User’s Manual
Hardware Description
XS47
XS57
XS67
XS77
XS87
a
(8:4) Register (Read/Write)
7
Transmit S
The S
With the transmit multiframe begin an interrupt ISR1.XMB is
generated and the contents of these registers XSA(8:4) is copied into
a shadow register. The contents is subsequently sent out in the
service words of the next outgoing CRC multiframe (or doubleframes)
if none of the time slot 0 transparent modes is enabled. XS40 is sent
out in bit position 4 in frame 1, XS47 in frame 15. The transmit
multiframe begin interrupt XMB request that these registers should be
serviced. If requests for new information are ignored, current contents
is repeated.
XS46
XS56
XS66
XS76
XS86
H
, 00
a
H
-bit register access is enabled by setting bit FMR1.ENSA = 1.
, 00
XS45
XS55
XS65
XS75
XS85
H
a
-Bit Data
, 00
H
, 00
XS44
XS54
XS64
XS74
XS84
H
254
XS43
XS53
XS63
XS73
XS83
XS42
XS52
XS62
XS72
XS82
XS41
XS51
XS61
XS71
XS81
DS1.1, 2003-10-23
PEF 2256 H/E
XS40
XS50
XS60
XS70
XS80
E1 Registers
0
FALC
(2C)
(2D)
(2E)
(2F)
(30)
®
56
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