PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 352

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

RAL1
Receive Address Byte Low Register 2 (Read/Write)
Value after reset: FF
RAL2
RAL2
Interrupt Port Configuration (Read/Write)
Value after reset: 00
IPC
Unused bits have to be cleared.
SSYF
IC0, IC1
User’s Manual
Hardware Description
7
7
Value of First Individual Low Address Byte
Value of the second individually programmable low address
byte.
Select SYNC Frequency
Only applicable in master mode (LIM0.MAS = 1) and bit CMR2.DCF
is cleared.
0
1
Interrupt Port Configuration
These bits define the function of the interrupt output stage (pin INT):
IC1
X
0
1
H
H
Reference clock on port SYNC is 1.544/2.048 MHz
(see LIM1.DCOC)
Reference clock on port SYNC is 8 kHz
IC0
0
1
1
Function
Open drain output
Push/pull output, active low
Push/pull output, active high
352
SSYF
IC1
DS1.1, 2003-10-23
T1/J1 Registers
PEF 2256 H/E
IC0
0
0
FALC
(07)
(08)
®
56