PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 261

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Line Interface Mode 2 (Read/Write)
Value after reset: 20
LIM2
SLT(1:0)
SCF
ELT
MPAS
User’s Manual
Hardware Description
7
0
Receive Slicer Threshold
00 = The receive slicer generates a mark (digital one) if the voltage
01 = The receive slicer generates a mark (digital one) if the voltage
10 = The receive slicer generates a mark (digital one) if the voltage
11 = The receive slicer generates a mark (digital one) if the voltage
Select Corner Frequency of DCO-R
Setting this bit reduces the corner frequency of the DCO-R circuit by
the factor of ten to 0.2 Hz.
Note: Reducing the corner frequency of the DCO-R circuitry
Note: LIM2.SCF is ignored, if CMR2.ECFAR is set.
Enable Loop-Timed
0 =
1 =
Multi-Purpose Analog Switch
This bit controls the analog switch between pins AS1 and AS2.
0 =
1 =
H
0
at RL1/2 exceeds 55% of the peak amplitude.
at RL1/2 exceeds 67% of the peak amplitude (recommended in
some T1/J1 applications).
at RL1/2 exceeds 50% of the peak amplitude (default,
recommended in E1 mode).
at RL1/2 exceeds 45% of the peak amplitude.
Normal operation
Transmit clock is generated from the clock supplied by MCLK
which is synchronized to the extracted receive route clock. In
this configuration the transmit elastic buffer has to be enabled.
Refer to register XSW.XTM. For correct operation of loop timed
the remote loop (bit LIM1.RL = 0) must be inactive and bit
CMR1.DXSS must be cleared.
Switch is open.
Switch is closed.
increases the synchronization time before the frequencies are
synchronized.
SLT1
SLT0
261
SCF
ELT
MPAS
DS1.1, 2003-10-23
PEF 2256 H/E
EOU
E1 Registers
0
FALC
(3A)
®
56