PEF2256 INFINEON [Infineon Technologies AG], PEF2256 Datasheet - Page 331

• Manufacturer Part Number: PEF2256
• Description: E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

RME2
RFS2
RDO2
ALLS2
User’s Manual
Hardware Description
Receive Message End - HDLC Channel 2
One complete message of length less than 32 bytes, or the last part
of a frame at least 32 bytes long is stored in the receive FIFO2,
including the status byte.
The complete message length can be determined reading register
RBC2, the number of bytes currently stored in RFIFO2 is given by
RBC2(6:0). Additional information is available in register RSIS2.
Receive Frame Start - HDLC Channel 2
This is an early receiver interrupt activated after the start of a valid
frame has been detected, i.e. after an address match (in operation
modes providing address recognition), or after the opening flag
(transparent mode 0) is detected, delayed by two bytes. After an
RFS2 interrupt, the contents of
• RAL1
• RSIS2 bits 3 to 1
are valid and can be read by the CPU.
Receive Data Overflow - HDLC Channel 2
This interrupt status indicates that the CPU did not respond fast
enough to an RPF2 or RME2 interrupt and that data in RFIFO2 has
been lost. Even when this interrupt status is generated, the frame
continues to be received when space in the RFIFO2 is available
again.
Note: Whereas the bit RSIS2.RDO2 in the frame status byte
All Sent - HDLC Channel 2
This bit is set if the last bit of the current frame has been sent
completely and XFIFO2 is empty. This bit is valid in HDLC mode only.
indicates whether an overflow occurred when receiving the
frame currently accessed in the RFIFO2, the ISR4.RDO2
interrupt status is generated as soon as an overflow occurs
and does not necessarily pertain to the frame currently
accessed by the processor.
331
DS1.1, 2003-10-23
PEF 2256 H/E
E1 Registers
FALC
®
56