PIC18C242 MICROCHIP [Microchip Technology], PIC18C242 Datasheet - Page 75

• Manufacturer Part Number: PIC18C242
• Description: High-Performance Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

7.0.6
External interrupts on the RB0/INT0, RB1/INT1 and
RB2/INT2 pins are edge triggered: either rising if the
corresponding INTEDGx bit is set in the INTCON2 reg-
ister, or falling, if the INTEDGx bit is clear. When a valid
edge appears on the RBx/INTx pin, the corresponding
flag bit INTxF is set. This interrupt can be disabled by
clearing the corresponding enable bit INTxE. Flag bit
INTxF must be cleared in software in the interrupt ser-
vice routine before re-enabling the interrupt. All exter-
nal interrupts (INT0, INT1 and INT2) can wake-up the
processor from SLEEP, if bit INTxE was set prior to
going into SLEEP. If the global interrupt enable bit GIE
set, the processor will branch to the interrupt vector fol-
lowing wake-up.
Interrupt priority for INT1 and INT2 is determined by the
value contained in the interrupt priority bits INT1IP
(INTCON3<6>) and INT2IP (INTCON3<7>). There is
no priority bit associated with INT0. It is always a high
priority interrupt source.
7.0.7
In 8-bit mode (which is the default), an overflow (FFh
00h) in the TMR0 register will set flag bit TMR0IF. In
16-bit mode, an overflow (FFFFh
EXAMPLE 7-1:
7/99 Microchip Technology Inc.
MOVWF
MOVFF
MOVFF
;
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
INT0 INTERRUPT
TMR0 INTERRUPT
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR located anywhere
; Restore BSR
; Restore WREG
; Restore STATUS
0000h) in the
Preliminary
TMR0H:TMR0L registers will set flag bit TMR0IF. The
interrupt can be enabled/disabled by setting/clearing
enable bit T0IE (INTCON<5>). Interrupt priority for
Timer0 is determined by the value contained in the
interrupt priority bit TMR0IP (INTCON2<2>). See Sec-
tion 8.0 for further details on the Timer0 module.
7.0.8
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<3>).
Interrupt priority for PORTB Interrupt on change is
determined by the value contained in the interrupt pri-
ority bit RBIP (INTCON2<0>).
7.1
During an interrupt, the return PC value is saved on the
stack. Additionally, the WREG, STATUS and BSR reg-
isters are saved on the fast return stack. If a fast return
from interrupt is not used (See Section 4.3), the user
may need to save the WREG, STATUS and BSR regis-
ters in software. Depending on the user’s application,
other registers may also need to be saved. Example 6-
1 saves and restores the WREG, STATUS and BSR
registers during an interrupt service routine.
PORTB INTERRUPT ON CHANGE
Context Saving During Interrupts
PIC18CXX2
DS39026B-page 75