PIC18C242 MICROCHIP [Microchip Technology], PIC18C242 Datasheet - Page 225

• Manufacturer Part Number: PIC18C242
• Description: High-Performance Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

RRNCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example 1:
Example 2:
7/99 Microchip Technology Inc.
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
REG
REG
WREG
REG
WREG
REG
Q1
=
=
=
=
=
=
register ’f’
Rotate Right f (no carry)
[ label ]
0
d
a
(f<n>)
(f<0>)
N,Z
The contents of register ’f’ are
rotated one bit to the right. If ’d’ is 0,
the result is placed in WREG. If ’d’
is 1, the result is placed back in
register 'f' (default). If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1,
then the bank will be selected as
per the BSR value (default).
1
1
RRNCF
RRNCF
Read
0100
Q2
1101 0111
1110 1011
?
1101 0111
1110 1011
1101 0111
f
[0,1]
[0,1]
255
dest<n-1>,
dest<7>
REG, 1, 0
REG, 0, 0
RRNCF f,d,a
00da
Process
Data
Q3
register f
ffff
destination
Write to
Q4
ffff
Preliminary
SETF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
Decode
REG
REG
Q1
register ’f’
Set f
[ label ] SETF
0
a
FFh
None
The contents of the specified regis-
ter are set to FFh. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1,
then the bank will be selected as
per the BSR value (default).
1
1
SETF
Read
0110
Q2
=
=
f
[0,1]
PIC18CXX2
255
f
0x5A
0xFF
100a
Process
Data
f,a
REG,1
Q3
DS39026B-page 225
ffff
register ’f’
Write
Q4
ffff