PIC18C242 MICROCHIP [Microchip Technology], PIC18C242 Datasheet - Page 47

• Manufacturer Part Number: PIC18C242
• Description: High-Performance Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

4.11
The need for a large general purpose memory space
dictates a RAM banking scheme. The data memory is
partitioned into sixteen banks.
addressing, the BSR should be configured for the
desired bank.
BSR<3:0> holds the upper 4 bits of the 12-bit RAM
address. The BSR<7:4> bits will always read ’0’s, and
writes will have no effect.
A
tion set to assist in selecting banks.
FIGURE 4-8:
MOVLB
7/99 Microchip Technology Inc.
Note 1: For register file map detail, see Table 4-1.
Bank Select Register (BSR)
bank select
instruction has been provided in the instruc-
2: The access bit of the instruction can be used to force an override of the selected bank
3: The MOVFF instruction embeds the entire 12-bit address in the instruction.
(BSR<3:0>) to the registers of the Access Bank.
DIRECT ADDRESSING
BSR<3:0>
(2)
When using direct
location select
7
Direct Addressing
Data
Memory
from opcode
(1)
(3)
Preliminary
(3)
000h
0FFh
Bank 0
00h
If the currently selected bank is not implemented, any
read will return all '0's and all writes are ignored. The
STATUS register bits will be set/cleared as appropriate
for the instruction performed.
Each Bank extends up to FFh (256 bytes). All data
memory is implemented as static RAM.
A MOVFF instruction ignores the BSR, since the 12-bit
addresses are embedded into the instruction word.
Section 4.12 provides a description of indirect address-
ing, which allows linear addressing of the entire RAM
space.
0
100h
1FFh
Bank 1
01h
PIC18CXX2
E00h
EFFh
Bank 14
0Eh
DS39026B-page 47
F00h
FFFh
Bank 15
0Fh