PIC18C242 MICROCHIP [Microchip Technology], PIC18C242 Datasheet - Page 21

• Manufacturer Part Number: PIC18C242
• Description: High-Performance Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

2.7
When the device executes a SLEEP instruction, the on-
chip clocks and oscillator are turned off and the device
is held at the beginning of an instruction cycle (Q1
state). With the oscillator off, the OSC1 and OSC2 sig-
nals will stop oscillating. Since all the transistor switch-
TABLE 2-3:
2.8
Power up delays are controlled by two timers, so that no
external reset circuitry is required for most applications.
The delays ensure that the device is kept in RESET
until the device power supply and clock are stable. For
additional information on RESET operation, see the
“Reset” section.
The first timer is the Power-up Timer (PWRT), which
optionally provides a fixed delay of 72 ms (nominal) on
power-up only (POR and BOR). The second timer is
the Oscillator Start-up Timer OST, intended to keep the
chip in RESET until the crystal oscillator is stable.
RC
RCIO
ECIO
EC
LP, XT, and HS
See Table 3-1, in the “Reset” section, for time-outs due to Sleep and MCLR reset.
7/99 Microchip Technology Inc.
Effects of Sleep Mode on the On-chip
Oscillator
Power-up Delays
OSC Mode
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Floating, external resistor should pull
high
Floating, external resistor should pull
high
Floating
Floating
Feedback inverter disabled, at quies-
cent voltage level
Preliminary
OSC1 Pin
ing currents have been removed, sleep mode achieves
the lowest current consumption of the device (only
leakage currents). Enabling any on-chip feature that
will operate during sleep will increase the current con-
sumed during sleep. The user can wake from SLEEP
through external reset, Watchdog Timer Reset or
through an interrupt.
With the PLL enabled (HS/PLL oscillator mode), the
time-out sequence following a power-on reset is differ-
ent from other oscillator modes. The time-out sequence
is as follows: First the PWRT time-out is invoked after a
POR time delay has expired. Then the Oscillator Start-
up Timer (OST) is invoked. However, this is still not a
sufficient amount of time to allow the PLL to lock at high
frequencies. The PWRT timer is used to provide an
additional fixed 2ms (nominal) time-out to allow the PLL
ample time to lock to the incoming clock frequency.
At logic low
Configured as Port A, bit 6
Configured as Port A, bit 6
At logic low
Feedback inverter disabled, at quies-
cent voltage level
PIC18CXX2
OSC2 Pin
DS39026B-page 21