PIC18C242 MICROCHIP [Microchip Technology], PIC18C242 Datasheet - Page 139

• Manufacturer Part Number: PIC18C242
• Description: High-Performance Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

14.3.8
Transmission of a data byte, a 7-bit address or the other
half of a 10-bit address is accomplished by simply writ-
ing a value to the SSPBUF register. This action will set
the buffer full flag bit, BF, and allow the baud rate gen-
erator to begin counting and start the next transmis-
sion. Each bit of address/data will be shifted out onto
the SDA pin after the falling edge of SCL is asserted
(see data hold time specification
is held low for one baud rate generator roll over count
(T
high (see Data setup time specification
107). When the SCL pin is released high, it is held that
way for T
stable for that duration and some hold time after the
next falling edge of SCL. After the eighth bit is shifted
out (the falling edge of the eighth clock), the BF flag is
cleared and the master releases SDA. allowing the
slave device being addressed to respond with an ACK
bit during the ninth bit time, if an address match occurs
or if data was received properly. The status of ACK is
written into the ACKDT bit on the falling edge of the
ninth clock. If the master receives an acknowledge, the
acknowledge status bit, ACKSTAT, is cleared. If not, the
bit is set. After the ninth clock, the SSPIF bit is set and
the master clock (baud rate generator) is suspended
until the next data byte is loaded into the SSPBUF, leav-
ing SCL low and SDA unchanged (Figure 14-18).
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL until all seven
address bits and the R/W bit are completed. On the fall-
ing edge of the eighth clock, the master will de-assert
the SDA pin allowing the slave to respond with an
acknowledge. On the falling edge of the ninth clock, the
master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2<6>).
Following the falling edge of the ninth clock transmis-
sion of the address, the SSPIF is set, the BF flag is
cleared and the baud rate generator is turned off until
another write to the SSPBUF takes place, holding SCL
low and allowing SDA to float.
14.3.8.1
In transmit mode, the BF bit (SSPSTAT<0>) is set when
the CPU writes to SSPBUF and is cleared when all 8
bits are shifted out.
BRG
7/99 Microchip Technology Inc.
). Data should be valid before SCL is released
I
BRG
2
C MASTER MODE TRANSMISSION
BF STATUS FLAG
. The data on the SDA pin must remain
parameter
106). SCL
parameter
Preliminary
14.3.8.2
If the user writes the SSPBUF when a transmit is
already in progress, (i.e. SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
14.3.8.3
In transmit mode, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an acknowledge
(ACK = 0), and is set when the slave does not acknowl-
edge (ACK = 1). A slave sends an acknowledge when
it has recognized its address (including a general call)
or when the slave has properly received its data.
14.3.9
Master mode reception is enabled by programming the
receive enable bit, RCEN (SSPCON2<3>).
The baud rate generator begins counting, and on each
rollover, the state of the SCL pin changes (high to low/
low to high) and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag bit is
set, the SSPIF flag bit is set and the baud rate genera-
tor is suspended from counting, holding SCL low. The
MSSP is now in IDLE state, awaiting the next com-
mand. When the buffer is read by the CPU, the BF flag
bit is automatically cleared. The user can then send an
acknowledge bit at the end of reception, by setting the
acknowledge
(SSPCON2<4>).
14.3.9.1
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
14.3.9.2
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.
14.3.9.3
If the user writes the SSPBUF when a receive is
already in progress (i.e. SSPSR is still shifting in a data
byte), the the WCOL bit is set and the contents of the
buffer are unchanged (the write doesn’t occur).
Note:
I
2
C MASTER MODE RECEPTION
WCOL STATUS FLAG
ACKSTAT STATUS FLAG
The MSSP Module must be in an IDLE
STATE before the RCEN bit is set, or the
RCEN bit will be disregarded.
BF STATUS FLAG
SSPOV STATUS FLAG
WCOL STATUS FLAG
sequence
PIC18CXX2
enable
DS39026B-page 139
bit
ACKEN