PIC18C242 MICROCHIP [Microchip Technology], PIC18C242 Datasheet - Page 128

• Manufacturer Part Number: PIC18C242
• Description: High-Performance Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18CXX2
TABLE 14-2:
14.3
The MSSP module in I
master and slave functions (including general call sup-
port) and provides interrupts on start and stop bits in
hardware to determine a free bus (multi-master func-
tion). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer. These are the RC3/
SCK/SCL pin, which is the clock (SCL), and the RC4/
SDI/SDA pin, which is the data (SDA). The user must
configure these pins as inputs or outputs through the
TRISC<4:3> bits.
The MSSP module functions are enabled by setting
MSSP Enable bit SSPEN (SSPCON<5>).
DS39026B-page 128
INTCON
PIR1
PIE1
IPR1
TRISC
SSPBUF
SSPCON
TRISA
SSPSTAT
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
Name
MSSP I
Shaded cells are not used by the MSSP in SPI mode.
PORTC Data Direction Register
PSPIF
PSPIE
PSPIP
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
GIEH
Bit 7
SMP
GIE/
—
2
REGISTERS ASSOCIATED WITH SPI OPERATION
C Operation
(1)
(1)
(1)
PORTA Data Direction Register
SSPOV SSPEN
2
PEIE/
GIEL
ADIF
ADIE
ADIP
Bit 6
CKE
C mode fully implements all
TMR0IE INT0IE
RCIE
RCIP
RCIF
Bit 5
D/A
Bit 4
TXIF
TXIE
TXIP
CKP
P
Preliminary
SSPM3
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
S
FIGURE 14-7: MSSP BLOCK DIAGRAM
The MSSP module has six registers for I
These are the:
• MSSP Control Register1 (SSPCON1)
• MSSP Control Register2 (SSPCON2)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• MSSP Shift Register (SSPSR) - Not directly
• MSSP Address Register (SSPADD)
TMR0IF
CCP1IF
CCP1IE
CCP1IP
SSPM2
RC3/SCK/SCL
accessible
Bit 2
RC4/
SDI/
SDA
R/W
TMR2IF TMR1IF
TMR2IE TMR1IE
TMR2IP TMR1IP
SSPM1
INT0IF
Bit 1
UA
Read
Shift
Clock
(I
2
MSb
C MODE)
SSPM0
RBIF
Bit 0
Stop bit detect
SSPBUF reg
Match detect
SSPADD reg
BF
SSPSR reg
Start and
7/99 Microchip Technology Inc.
0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
--11 1111 --11 1111
0000 0000 0000 0000
Value on
POR,
BOR
LSb
Write
Internal
Data Bus
(SSPSTAT reg)
2
C operation.
Set, Reset
S, P bits
Addr Match
Value on
all other
resets