PIC18C242 MICROCHIP [Microchip Technology], PIC18C242 Datasheet - Page 38

• Manufacturer Part Number: PIC18C242
• Description: High-Performance Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18CXX2
4.6
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g. GOTO)
then two cycles are required to complete the instruction
(Example 4-2).
EXAMPLE 4-2:
4.7
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The least significant byte of an instruction
word is always stored in a program memory location
with an even address (LSB = ’0’). Figure 4-5 shows an
example of how instruction words are stored in the pro-
gram memory. To maintain alignment with instruction
boundaries, the PC increments in steps of 2 and the
LSB will always read ’0’. (See Section 4.4)
The CALL and GOTO instructions have an absolute
program memory address embedded into the instruc-
tion. Since instructions are always stored on word
FIGURE 4-5:
DS39026B-page 38
1. MOVLW 55h
2. MOVWF PORTB
3. BRA
4. BSF
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
Instruction Flow/Pipelining
Instructions in Program Memory
SUB_1
PORTA, BIT3 (Forced NOP)
Instruction 1:
Instruction 2:
Instruction 3:
INSTRUCTIONS IN PROGRAM MEMORY
INSTRUCTION PIPELINE FLOW
Program Memory
Byte Locations
MOVLW
GOTO
MOVFF
Fetch 1
Tcy0
055h
000006h
123h, 456h
Execute 1
Fetch 2
Tcy1
Preliminary
Execute 2
Fetch 3
LSB = 1
Tcy2
0Fh
EFh
F0h
C1h
F4h
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register" (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
boundaries, the data contained in the instruction is a
word address. The word address is written to
PC<20:1>, which accesses the desired byte address
in program memory. Instruction #2 in Figure 4-5
shows how the instruction "GOTO
encoded in the program memory. Program branch
instructions which encode a relative address offset
operate in the same manner. The offset value stored
in a branch instruction represents the number of sin-
gle word instructions that the PC will be offset by.
Section 19.0 provides further details of the instruction
set.
Execute 3
Fetch 4
LSB = 0
Tcy3
55h
03h
00h
23h
56h
Fetch SUB_1 Execute SUB_1
Word Address
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
Flush
Tcy4
7/99 Microchip Technology Inc.
Tcy5
000006h’ is