PIC18C242 MICROCHIP [Microchip Technology], PIC18C242 Datasheet - Page 118

• Manufacturer Part Number: PIC18C242
• Description: High-Performance Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

bit 7
bit 6
bit 0
PIC18CXX2
14.2
The MSSP module has three associated registers.
These include a status register and two control regis-
ters.
Register 14-1: SSPSTAT: MSSP Status Register
bit 5
bit 4
bit 3
bit 2
bit 1
DS39026B-page 118
Control Registers
bit 7
SMP: Sample bit
SPI Master Mode
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave Mode
SMP must be cleared when SPI is used in slave mode
In I
1= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0= Slew rate control enabled for high speed mode (400 kHz)
CKE: SPI Clock Edge Select
CKP = 0
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
D/A: Data/Address bit (I
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: Stop bit
(I
1 = Indicates that a stop bit has been detected last (this bit is ’0’ on RESET)
0 = Stop bit was not detected last
S: Start bit
(I
1 = Indicates that a start bit has been detected last (this bit is ’0’ on RESET)
0 = Start bit was not detected last
R/W: Read/Write bit information (I
This bit holds the R/W bit information following the last address match. This bit is only valid from the address
match to the next start bit, stop bit, or not ACK bit.
In I
1 = Read
0 = Write
In I
1 = Transmit is in progress
0 = Transmit is not in progress.
OR-ing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in IDLE mode.
UA: Update Address (10-bit I
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
BF: Buffer Full Status bit
Receive (SPI and I
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I
1 = Data Transmit in progress (does not include the ACK and stop bits), SSPBUF is full
0 = Data Transmit complete (does not include the ACK and stop bits), SSPBUF is empty
Legend:
R = Readable bit
- n = Value at POR reset
2
2
R/W-0
C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared)
C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared)
SMP
2
2
2
C master or slave mode:
C slave mode:
C master mode:
2
C mode only)
R/W-0
CKE
2
C modes)
2
C mode only)
2
C mode only)
2
R-0
D/A
W = Writable bit
’1’ = Bit is set
C mode only)
Preliminary
R-0
P
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
R-0
S
R/W
R-0
x = Bit is unknown
R-0
UA
7/99 Microchip Technology Inc.
bit 0
R-0
BF