PIC18C242 MICROCHIP [Microchip Technology], PIC18C242 Datasheet - Page 222

• Manufacturer Part Number: PIC18C242
• Description: High-Performance Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18CXX2
RETFIE
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
DS39026B-page 222
After Interrupt
operation
Decode
No
PC
W
BSR
STATUS
GIE/GIEH, PEIE/GIEL=
Q1
operation
operation
Return from Interrupt
[ label ]
s
(TOS)
1
if s = 1
(WS)
(STATUSS)
(BSRS)
PCLATU, PCLATH are unchanged.
GIE/GIEH,PEIE/GIEL.
Return from Interrupt. Stack is
popped and Top of Stack (TOS) is
loaded into the PC. Interrupts are
enabled by setting the either the
high or low priority global inter-
rupt enable bit. If ’s’ = 1, the con-
tents of the shadow registers WS,
STATUSS and BSRS are loaded
into their corresponding registers,
WREG, STATUS and BSR. If ’s’ =
0, no update of these registers
occurs (default).
1
2
RETFIE
0000
No
No
Q2
[0,1]
GIE/GIEH or PEIE/GIEL,
WREG,
PC,
1
RETFIE s
0000
BSR,
operation
operation
=
=
=
=
STATUS,
No
No
Q3
TOS
WS
BSRS
STATUSS
1
0001
pop PC from
Set GIEH or
operation
stack
GIEL
No
Q4
000s
Preliminary
RETLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
TABLE
CALL TABLE ; WREG contains table
:
ADDWF PCL
RETLW k0
RETLW k1
:
:
RETLW kn
Before Instruction
After Instruction
operation
Decode
WREG
WREG
No
Q1
;
;
;
; Begin table
;
; End of table
; WREG = offset
=
=
operation
table value
Return Literal to WREG
[ label ]
0
k
(TOS)
PCLATU, PCLATH are unchanged
None
WREG is loaded with the eight bit
literal 'k'. The program counter is
loaded from the top of the stack
(the return address). The high
address latch (PCLATH) remains
unchanged.
1
2
literal ’k’
offset value
WREG now has
Read
0000
No
Q2
0x07
value of kn
k
WREG,
7/99 Microchip Technology Inc.
255
PC,
RETLW k
1100
operation
Process
Data
No
Q3
kkkk
pop PC from
stack, Write
to WREG
operation
No
Q4
kkkk