PIC18C242 MICROCHIP [Microchip Technology], PIC18C242 Datasheet - Page 153

• Manufacturer Part Number: PIC18C242
• Description: High-Performance Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

15.1
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In asynchronous
mode, bit BRGH (TXSTA<2>) also controls the baud
rate. In synchronous mode, bit BRGH is ignored.
Table 15-1 shows the formula for computation of the
baud rate for different USART modes, which only apply
in master mode (internal clock).
Given the desired baud rate and Fosc, the nearest inte-
ger value for the SPBRG register can be calculated
using the formula in Table 15-1. From this, the error in
baud rate can be determined.
Example 15-1 shows the calculation of the baud rate
error for the following conditions:
EXAMPLE 15-1: CALCULATING BAUD RATE ERROR
TABLE 15-1:
X = value in SPBRG (0 to 255)
TABLE 15-2:
Name
TXSTA
RCSTA
SPBRG
Legend: x = unknown, - = unimplemented read as '0'.
Desired Baud rate
Solving for X:
Calculated Baud Rate
Error
7/99 Microchip Technology Inc.
SYNC
0
1
F
Desired Baud Rate = 9600
BRGH = 0
SYNC = 0
OSC
USART Baud Rate Generator (BRG)
X
X
X
Shaded cells are not used by the BRG.
Baud Rate Generator Register
= 16 MHz
CSRC
SPEN
Bit 7
BAUD RATE FORMULA
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
(Asynchronous) Baud Rate = F
(Synchronous) Baud Rate = F
Bit 6
RX9
TX9
= Fosc / (64 (X + 1))
= ( (Fosc / Desired Baud rate) / 64 ) - 1
= ((16000000 / 9600) / 64) - 1
= [25.042] = 25
= 16000000 / (64 (25 + 1))
= 9615
= (Calculated Baud Rate - Desired Baud Rate)
= (9615 - 9600) / 9600
= 0.16%
BRGH = 0 (Low Speed)
SREN
TXEN
Bit 5
SYNC
CREN
Desired Baud Rate
Bit 4
Preliminary
Bit 3
OSC
OSC
—
—
/(64(X+1))
/(4(X+1))
BRGH
FERR
Bit 2
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the F
baud rate error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before output-
ting the new baud rate.
15.1.1
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
OERR
TRMT
Bit 1
SAMPLING
OSC
RX9D 0000 -00x
TX9D
Bit 0
/(16(X + 1)) equation can reduce the
Baud Rate= F
BRGH = 1 (High Speed)
0000 -010
0000 0000
PIC18CXX2
Value on
POR,
BOR
NA
OSC
DS39026B-page 153
/(16(X+1))
0000 -010
0000 -00x
0000 0000
other resets
Value on all