PIC18C242 MICROCHIP [Microchip Technology], PIC18C242 Datasheet - Page 107

• Manufacturer Part Number: PIC18C242
• Description: High-Performance Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

12.2
The Timer1 oscillator may be used as the clock source
for Timer3. The Timer1 oscillator is enabled by setting
the T1OSCEN (T1CON<3>) bit. The oscillator is a low
power oscillator rated up to 200 KHz. See Section 10.0
for further details.
12.3
The TMR3 Register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR3 Interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit TMR3IF (PIR2<1>).
This interrupt can be enabled/disabled by setting/clear-
ing TMR3 interrupt enable bit TMR3IE (PIE2<1>).
TABLE 12-1:
INTCON
PIR2
PIE2
IPR2
TMR3L
TMR3H
T1CON
T3CON
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by the Timer1 module.
Name
7/99 Microchip Technology Inc.
Timer1 Oscillator
Timer3 Interrupt
Holding register for the Least Significant Byte of the 16-bit TMR3 register
Holding register for the Most Significant Byte of the 16-bit TMR3 register
Bit 7
GIEH
GIE/
—
—
—
—
—
REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
T3CKPS2
PEIE/
Bit 6
GIEL
—
—
—
—
T1CKPS1
T3CKPS1
TMR0IE
Bit 5
—
—
—
T1CKPS0
T3CKPS0
INT0IE
Bit 4
—
—
—
Preliminary
T1OSCEN
T3CCP1
BCLIF
BCLIE
BCLIP
Bit 3
RBIE
12.4
If the CCP module is configured in compare mode to
generate a “special event trigger" (CCP1M3:CCP1M0
= 1011), this signal will reset Timer3.
Timer3 must be configured for either timer or synchro-
nized counter mode to take advantage of this feature. If
Timer3 is running in asynchronous counter mode, this
reset operation may not work. In the event that a write
to Timer3 coincides with a special event trigger from
CCP1, the write will take precedence. In this mode of
operation, the CCPR1H:CCPR1L registers pair effec-
tively becomes the period register for Timer3.
Note:
T1SYNC
T3SYNC
TMR0IF
LVDIE
LVDIP
LVDIF
Bit 2
Resetting Timer3 Using a CCP Trigger
Output
The special event triggers from the CCP
module will not set interrupt flag bit
TMR3IF (PIR1<0>).
TMR1CS
TMR3CS
TMR3IE
TMR3IP
TMR3IF
INT0IF
Bit 1
PIC18CXX2
TMR1ON
TMR3ON
CCP2IF
CCP2IE
CCP2IP
Bit 0
RBIF
DS39026B-page 107
--00 0000
0000 000x
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
-000 0000
Value on
POR,
BOR
--uu uuuu
0000 000u
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
-uuu uuuu
Value on
all other
resets