PIC18C242 MICROCHIP [Microchip Technology], PIC18C242 Datasheet - Page 187

• Manufacturer Part Number: PIC18C242
• Description: High-Performance Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

18.3
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared, but
keeps running, the PD bit (RCON<3>) is cleared, the
TO (RCON<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either V
cuitry is drawing current from the I/O pin, power-down
the A/D and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid switching currents caused by floating inputs. The
T0CKI input should also be at V
current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (V
18.3.1
The device can wake up from SLEEP through one of
the following events:
1.
2.
3.
The following peripheral interrupts can wake the device
from SLEEP:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Other peripherals cannot generate interrupts, since
during SLEEP, no on-chip clocks are present.
7/99 Microchip Technology Inc.
External reset input on MCLR pin.
Watchdog Timer Wake-up (if WDT was
enabled).
Interrupt from INT pin, RB port change or a
Peripheral Interrupt.
PSP read or write.
TMR1 interrupt. Timer1 must be operating as
an asynchronous counter.
TMR3 interrupt. Timer3 must be operating as
an asynchronous counter.
CCP capture mode interrupt.
Special event trigger (Timer1 in asynchronous
mode using an external clock).
MSSP (Start/Stop) bit detect interrupt.
MSSP transmit or receive in slave mode (SPI/
I
USART RX or TX (synchronous slave mode).
A/D conversion (when A/D clock source is RC).
2
C).
Power-down Mode (SLEEP)
WAKE-UP FROM SLEEP
DD
or V
SS
, ensure no external cir-
DD
or V
SS
for lowest
IHMC
).
Preliminary
External MCLR Reset will cause a device reset. All
other events are considered a continuation of program
execution and will cause a "wake-up". The TO and PD
bits in the RCON register can be used to determine the
cause of the device reset. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared, if a WDT time-out occurred (and caused
wake-up).
When the SLEEP instruction is being executed, the next
instruction (PC + 2) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
PIC18CXX2
DS39026B-page 187