PIC18C242 MICROCHIP [Microchip Technology], PIC18C242 Datasheet - Page 70

• Manufacturer Part Number: PIC18C242
• Description: High-Performance Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18CXX2
7.0.2
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to he number of peripheral
interrupt sources, there are two Peripheral Interrupt
Flag Registers (PIR1, PIR2).
Register 7-4:
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS39026B-page 70
Note 1: Interrupt flag bits get set when an interrupt
Note 2: User software should ensure the appropri-
PIR REGISTERS
bit 7
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (16CXXX compatibility mode)
LWRT: Long Write Enable
For details of bit operation see Register 4-1
Unimplemented: Read as ’0’
RI: Reset Instruction Flag bit
For details of bit operation see Register 4-1
TO: Watchdog Time-out Flag bit
For details of bit operation see Register 4-1
PD: Power-down Detection Flag bit
For details of bit operation see Register 4-1
POR: Power-on Reset Status bit
For details of bit operation see Register 4-1
BOR: Brown-out Reset Status bit
For details of bit operation see Register 4-1
Legend:
R = Readable bit
- n = Value at POR reset
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
ate interrupt flag bits are cleared prior to
enabling an interrupt, and after servicing
that interrupt.
R/W-0
IPEN
RCON Register
R/W-0
LWRT
U-0
W = Writable bit
’1’ = Bit is set
—
R/W-1
Preliminary
RI
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
R/W-1
7.0.3
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of periph-
eral interrupt sources, there are two Peripheral Inter-
rupt Enable Registers (PIE1, PIE2). When IPEN = 0,
the PEIE bit must be set to enable any of these periph-
eral interrupts.
7.0.4
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to on the number of
peripheral interrupt sources, there are two Peripheral
Interrupt Priority Registers (IPR1, IPR2). The operation
of the priority bits requires that the Interrupt Priority
Enable (IPEN) bit be set.
7.0.5
The RCON register contains the bit which is used to
enable prioritized interrupts (IPEN).
TO
PIE REGISTERS
IPR REGISTERS
RCON REGISTER
R/W-1
PD
x = Bit is unknown
R/W-0
POR
7/99 Microchip Technology Inc.
bit 0
R/W-0
BOR