tc59ym916bkg24a ETC-unknow, tc59ym916bkg24a Datasheet - Page 8

• Manufacturer Part Number: tc59ym916bkg24a
• Description: The Second Generation 512-megabit Xdrtm Dram
• Manufacturer: ETC-unknow

Block Diagram
blocks.
clock signals: 1/t
and CFMN signals. These virtual signals show the effective data rate of the logic blocks to which they connect; they
are not necessarily present in the actual memory component.
indicated by the 2/t
packet. These 24 bits are loaded into a register (clocked by the 1/t
Block. The VREF pin supplies a reference voltage used by the RQ receivers.
addresses for an activate (ACT) command, the bank (BR) and row (REFr) addresses for a precharge (PRE)
command, the bank (BP) address for a precharge (PRE) command, the bank (BR) address for a refresh precharge
(REFP) command, and the bank (BC) and column (C and SC) addresses for a read (RD) or write (WR or WRM)
command. In addition, a mask (M) is used for a masked write (WRM) command.
request. The control signals of the commands are loaded into registers and presented to the memory core. These
registers are clocked at maximum rates determined by core timing parameters, in this case 1/t
(1/4, 1/4, and 1/2 the frequency of CFM). These registers may be loaded at any t
they should not be changed until a t
to settle.
the associated sense amp array for the bank. Sensing a row is also referred to as “opening a page” for the bank.
precharged to a state in which a subsequent ACT command can be applied. Precharging a bank is also called
“closing the page” for the bank.
write (WR) column commands. These commands permit the data in the bank’s associated sense amp array to be
accessed.
selected bank is written with the data received from the DQ15…DQ0 pins.
amp array is read. The data is transmitted onto the DQ15...DQ0 pins.
in one t
assembles the 16x16-bit write data packet. The write data is then driven to the selected Sense Amp Array Bank.
pins transmit this read data packet (Q) in one t
connected to the 16:1 Mux Block. The VTERM pin supplies a termination voltage for the DQ pins.
control needed to write the control registers. The read data for these registers is accessed through the SDO/SDI
pins. These pins are also used to initialize the device.
speed transmit and receive circuits of the device. The control registers also supply bank (REFB) and row (REFr)
addresses for refresh operations.
A block diagram of the XDR DRAM device is shown in Figure 2. It shows all interface pins and major internal
The CFM and CFMN clock signals are received and used by the clock generation logic to produce three virtual
The RQ11...RQ0 pins receive the request packet. Two 12-bit words are received in one t
Three sets of control signals are produced by the Decode Block. These include the bank (BA) and row (R)
These commands can all be optionally delayed in increments of t
A bank address is decoded for an ACT command. The indicated row of the selected bank is sensed and placed into
Another bank address is decoded for a PRE command. The indicated bank and associated sense amp array are
After a bank is given an ACT command and before it is given a PRE command, it may receive read (RD) and
For a WR command, the bank address is decoded. The indicated column of the associated sense amp array of the
The bank address is decoded for a RD command. The indicated column of the selected bank’s associated sense
The DQ15...DQ0 pins receive the write data packet (D) for a write transaction. 16 sixteen-bit words are received
16 sixteen-bit words are accessed in the selected Sense Amp Array Bank for a read transaction. The DQ15…0
The RST, SCK, and CMD pins connect to the Control Register block. These pins supply the data, address and
The controls registers are used to transition between power modes, and are also used for calibrating the high
CC
interval. This is indicated by the 16/t
CYCLE
CYCLE
, 2/t
clocking signal connected to the 1: 2 Demux Block that assembles the 24-bit request
CYCLE
, and 16/t
RR
, t
PP
CC
, or t
. The frequency of these signals are 1x, 2x, and 8x that of the CFM
CC
CC
CC
TC59YM916BKG24A,32A,32B,40B,32C,40C
interval. This is indicated by the 16/t
clocking signal connected to the 1:16 Demux Block that
time later because timing paths of the memory core need time
CYCLE
CYCLE
clocking signal) and decoded by the Decode
under control of delay fields in the
CYCLE
rising edge. Once loaded,
CC
CYCLE
clocking signal
2004-12-15 8/76
RR
interval. This is
, 1/t
PP
Rev 0.1
, and 1/t
CC