tc59ym916bkg24a ETC-unknow, tc59ym916bkg24a Datasheet - Page 50

• Manufacturer Part Number: tc59ym916bkg24a
• Description: The Second Generation 512-megabit Xdrtm Dram
• Manufacturer: ETC-unknow

XDR DRAM Pattern Load with WDSL Register
beginning Receive Timing Calibration (RX TCAL). The method employed by the XDR DRAMs to achieve this is
called Write Data Serial Load (WDSL). A WDSL packet sends one-byte of serial data which is serially shifted into a
holding register within the XDR DRAM. Initialization software sends a sequence of WDSL packets, each of which
shifts the new byte in and advances the shifter by 8 positions. In this way, XDR DRAMs of varying widths can be
loaded with a single command type.
XDR DRAM. Depending upon the ratio of native device width to programmed width, there may be more than one
sub-column per column. After loading a full column, a series of WR commands will be issued to sequentially
transfer each sub-column of the column to the XDR DRAM core (s), based upon the SC [3:0] bits.
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
DQ2
DQ0
DQ1
DQ3
The XDR memory system requires a method of deterministically loading pattern data to XDR DRAMs before
Each sequence of WDSL packets will load one full column of data to the internal holding register of the target
×4
Table 10. WDSL-to-Core/DQ/SC Map (First Generation ×16/×8/×4 XDR DRAM, BL = 16)
DQ Pin Used
DQ6
DQ2
DQ4
DQ0
DQ3
DQ7
DQ3
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
×8
PHYSICAL VIEW OF XDR DRAM
LOGICAL VIEW OF XDR DRAM
DQ10
DQ12
DQ13
DQ14
DQ15
DQ14
DQ10
DQ12
DQ15
DQ15
DQ11
DQ11
DQ11
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ6
DQ2
DQ4
DQ8
DQ0
DQ3
DQ7
DQ3
DQ7
×16
WD [0] [15:0]
WD [1] [15:0]
WD [2] [15:0]
WD [3] [15:0]
WD [4] [15:0]
WD [5] [15:0]
WD [6] [15:0]
WD [7] [15:0]
WD [8] [15:0]
WD [9] [15:0]
WD [10] [15:0]
WD [12] [15:0]
WD [13] [15:0]
WD [14] [15:0]
WD [15] [15:0]
WD [14] [15:0]
WD [6] [15:0]
WD [10] [15:0]
WD [2] [15:0]
WD [12] [15:0]
WD [4] [15:0]
WD [8] [15:0]
WD [0] [15:0]
WD [1] [15:0]
WD [9] [15:0]
WD [5] [15:0]
WD [13] [15:0]
WD [3] [15:0]
WD [11] [15:0]
WD [7] [15:0]
WD [15] [15:0]
WD [11] [15:0]
Core Word
WDSL Word 15
WDSL Word 14
WDSL Word 13
WDSL Word 12
WDSL Word 11
WDSL Word 10
WDSL Word 9
WDSL Word 8
WDSL Word 7
WDSL Word 6
WDSL Word 5
WDSL Word 4
WDSL Word 3
WDSL Word 1
WDSL Word 0
WDSL Core Word
WDSL Word 8
WDSL Word 7
WDSL Word 12
WDSL Word 3
WDSL Word 10
WDSL Word 5
WDSL Word 14
WDSL Word 1
WDSL Word 9
WDSL Word 6
WDSL Word 13
WDSL Word 2
WDSL Word 11
WDSL Word 4
WDSL Word 15
WDSL Word 0
WDSL Word 2
WD [n] [15:0]
Load Order
SC[3:2]=xx
TC59YM916BKG24A,32A,32B,40B,32C,40C
×16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SC[3:2]=0x SC[3:2]=1x SC[3:2]=00 SC[3:2]=01 SC[3:2]=10 SC[3:2]=11
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
Word Written (1 = Written, 0 = Not Written)
Word Written (1 = Written, 0 = Not Written)
×8
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
1
1
0
0
0
1
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
2004-12-15 50/76
×4
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
Rev 0.1
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1