tc59ym916bkg24a ETC-unknow, tc59ym916bkg24a Datasheet - Page 53

• Manufacturer Part Number: tc59ym916bkg24a
• Description: The Second Generation 512-megabit Xdrtm Dram
• Manufacturer: ETC-unknow

conversion (demux block) in the data receiver block and before the parallel-to-serial conversion (mux block) in the
data transmitter block (see the block diagram in Figure 2 also). The block diagram is shown in this manner so the
functionality of the logic can be made as clear as possible. Some implementations may place this logic in the data
receiver and transmitter blocks, performing the mapping in Figure 50 on the serial data rather than the parallel
data. However, this design choice will not affect the functionality of the Dynamic Width logic; it is strictly an
implementation decision.
Figure 50. D-to-S and S-to-Q Mapping for Dynamic Width Control
The block diagram in Figure 49 indicates that the Dynamic Width logic is positioned after the serial-to-parallel
WIDTH [2:0] = 000 (×1 device width)
SC [3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
S [10] [15:0]
S [11] [15:0]
S [12] [15:0]
S [13] [15:0]
S [14] [15:0]
S [15] [15:0]
D [0] [15:0]
Q [0] [15:0]
S [0] [15:0]
S [1] [15:0]
S [2] [15:0]
S [3] [15:0]
S [4] [15:0]
S [5] [15:0]
S [6] [15:0]
S [7] [15:0]
S [8] [15:0]
S [9] [15:0]
WIDTH [2:0] = 001 (×2 device width)
WIDTH [2:0] = 010 (×4 device width)
SC [3:0]
SC [3:0]
000x
001x
010x
011x
100x
101x
110x
111x
00xx
01xx
10xx
11xx
TC59YM916BKG24A,32A,32B,40B,32C,40C
S [11:10] [15:0]
S [13:12] [15:0]
S [15:14] [15:0]
S [15:12] [15:0]
S [11:8] [15:0]
Q [1:0] [15:0]
Q [3:0] [15:0]
S [1:0] [15:0]
S [3:2] [15:0]
S [5:4] [15:0]
S [7:6] [15:0]
S [9:8] [15:0]
D [1:0] [15:0]
S [3:0] [15:0]
S [7:4] [15:0]
D [3:0] [15:0]
WIDTH [2:0] = 011 (×8 device width)
WIDTH [2:0] = 100 (×16 device width)
SC [3:0]
SC [3:0]
0xxx
1xxx
xxxx
D [15:0] [15:0]
Q [15:0] [15:0]
2004-12-15 53/76
S [15:8] [15:0]
S [15:0] [15:0]
D [7:0] [15:0]
Q [7:0] [15:0]
S [7:0] [15:0]
Rev 0.1