tc59ym916bkg24a ETC-unknow, tc59ym916bkg24a Datasheet - Page 6

• Manufacturer Part Number: tc59ym916bkg24a
• Description: The Second Generation 512-megabit Xdrtm Dram
• Manufacturer: ETC-unknow

TC59YM916BKG24A,32A,32B,40B,32C,40C
Table of Figures
Figure 1. XDR DRAM Device Write and Read Transactions-------------------------------------------------------- 3
Figure 2. 512Mb (8x4Mx16) XDR DRAM Block Diagram-------------------------------------------------------------- 9
Figure 3. Request Packet Formats----------------------------------------------------------------------------------------- 11
Figure 4. ACT-, RD-, WR-, PRE-to-ACT Packet Interactions------------------------------------------------------- 16
Figure 5. ACT-, RD-, WR-, PRE-to-RD Packet Interactions--------------------------------------------------------- 17
Figure 6. ACT-, RD-, WR-, PRE-to-WR Packet Interactions-------------------------------------------------------- 18
Figure 7. ACT-, RD-, WR-, PRE-to-PRE Packet Interactions------------------------------------------------------- 19
Figure 8. Request Scheduling Examples-------------------------------------------------------------------------------- 21
Figure 9. Write Transactions------------------------------------------------------------------------------------------------- 23
Figure 10. Read Transactions------------------------------------------------------------------------------------------------ 25
Figure 11. Interleaved Transactions--------------------------------------------------------------------------------------- 27
Figure 12. Write/Read Interaction------------------------------------------------------------------------------------------ 29
Figure 13. Propagation Delay------------------------------------------------------------------------------------------------ 32
Figure 14. Serial Write Transaction---------------------------------------------------------------------------------------- 34
Figure 15. Serial Read Transaction – Selected DRAM--------------------------------------------------------------- 34
Figure 16. Serial Read Transaction – Non-Selected DRAM-------------------------------------------------------- 34
Figure 17. Serial Identification (SID) Register-------------------------------------------------------------------------- 36
Figure 18. Configuration (CFG) Register--------------------------------------------------------------------------------- 36
Figure 19. Power Management (PM) Register-------------------------------------------------------------------------- 36
Figure 20. Write Data Serial Load (WDSL) Control Register------------------------------------------------------ 36
Figure 21. RQ Scan High (RQH) Register-------------------------------------------------------------------------------- 37
Figure 22. RQ Scan Low (RQL) Register--------------------------------------------------------------------------------- 37
Figure 23. Refresh Bank (REFB) Control Register-------------------------------------------------------------------- 37
Figure 24. Refresh High (REFH) Row Register------------------------------------------------------------------------- 37
Figure 25. Refresh Middle (REFM) Row Register--------------------------------------------------------------------- 37
Figure 26. Refresh Low (REFL) Row Register-------------------------------------------------------------------------- 38
Figure 27. IO Configuration (REFL) Register-------------------------------------------------------------------------- 38
Figure 28. Current Calibration 0 (CC0) Register----------------------------------------------------------------------- 38
Figure 29. Current Calibration 1 (CC1) Register----------------------------------------------------------------------- 38
Figure 30. Impedance Calibration 0 (ZC0) Register------------------------------------------------------------------ 38
Figure 31. Impedance Calibration 1 (ZC1) Register------------------------------------------------------------------ 39
Figure 32. Current Fuse Setting 0 (FZC0) Register------------------------------------------------------------------ 39
Figure 33. Current Fuse Setting 1 (FZC1) Register------------------------------------------------------------------ 39
Figure 34. Read Only Memory 0 (ROM0) Register-------------------------------------------------------------------- 39
Figure 35. Read Only Memory 1 (ROM1) Register-------------------------------------------------------------------- 39
Figure 36. Test Register------------------------------------------------------------------------------------------------------- 40
Figure 37. DLL Register-------------------------------------------------------------------------------------------------------- 40
Figure 38. PLL0 Register------------------------------------------------------------------------------------------------------ 40
Figure 39. PLL1 Register------------------------------------------------------------------------------------------------------ 40
Figure 40. IFT Register--------------------------------------------------------------------------------------------------------- 40
Figure 41. DA Register--------------------------------------------------------------------------------------------------------- 40
Figure 42. Partner-Definable (PART) Register-------------------------------------------------------------------------- 41
Figure 43. Delay (DLY) Control Register--------------------------------------------------------------------------------- 41
Figure 44. Refresh Transactions-------------------------------------------------------------------------------------------- 43
Figure 45. Calibration Transactions--------------------------------------------------------------------------------------- 44
Figure 46. Power State Management-------------------------------------------------------------------------------------- 46
Figure 47. Serial Interface Systems Topology------------------------------------------------------------------------- 47
Figure 48. Initialization Timing for XDR DRAM [ k ] Device-------------------------------------------------------- 47
Figure 49. Multiplexes for Dynamic Width Control------------------------------------------------------------------- 52
Figure 50. D-to-S and S-to-Q Mapping for Dynamic Width Control--------------------------------------------- 53
Figure 51. Byte Mask Logic--------------------------------------------------------------------------------------------------- 54
Figure 52. Write-Masked (WRM) Transaction Example-------------------------------------------------------------- 55
Figure 53. Write/Read Interaction – No ERAW Feature-------------------------------------------------------------- 56
Figure 54. Write/Read Interaction – ERAW Feature------------------------------------------------------------------ 56
Figure 55. XDR DRAM Block Diagram with Bank Sets-------------------------------------------------------------- 57
Figure 56. Simultaneous Precharge – tPP-D Cases------------------------------------------------------------------ 58
Figure 57. Clocking Waveforms--------------------------------------------------------------------------------------------- 65
Figure 58. RSL RQ Receive Waveform------------------------------------------------------------------------------------ 66
Figure 59. DRSL DQ Receive Waveform--------------------------------------------------------------------------------- 68
Figure 60. RSL DQ Transmit Waveforms--------------------------------------------------------------------------------- 70
Figure 61. Serial Interface Receive Waveforms------------------------------------------------------------------------ 71
Figure 62. Serial Interface Transmit Waveforms---------------------------------------------------------------------- 72
Figure 63. Equivalent Circuits for Package Parasitic---------------------------------------------------------------- 74
Figure 64. CSP x16 Package Mechanical Drawing-------------------------------------------------------------------- 75
Figure 65. CSP x16 Package - Pin Numbering (top view) ---------------------------------------------------------- 76
Rev 0.1
2004-12-15 6/76