tc59ym916bkg24a ETC-unknow, tc59ym916bkg24a Datasheet - Page 49

• Manufacturer Part Number: tc59ym916bkg24a
• Description: The Second Generation 512-megabit Xdrtm Dram
• Manufacturer: ETC-unknow

XDR DRAM Initialization Overview
[1] Apply voltage to VDD, VTERM and VREF pins. VTERM and VREF coltages must be less or equal to VDD
[2] Assert RST, SCK, SDI and CMD to logical zero. Then:
[3] XDR DRAM has valid Serial ID and all registers have default values that are defined in Figure 17 through
[4] Perform broadcast or directed register writes to adjust registers which need a value different from their default
[5] Perform Powerdown Exit sequence shown in Figure 46. This includes the activity from SCK cycle S
[6] Perform termination current calibration. The CALZ/CALE sequence shown in Figure 45 is issued 128 times,
[7] Condition the XDR DRAM banks by performing a REFA/REFI activate and REFP precharge operation to each
voltage at all times. Wait a time interval t
into low-power state.
Figure 42.
value.
final REFP command.
then the CALC/CALE sequence is issued 128 times. After this, each sequence is issued once every t
t
bank eight times. This can be interleaved to save time. The row address for the activate operation will step
through eight successive values of the REFr registers. The sequence between cycles T
Interleaved Refresh Example in Figure 44 could be performed eight times to satisfy this conditioning
requirement.
CALC
- Pulse SCK to logical one, then to logical zero four times.
- Assert RST to logical one. Reset circuit places XDR DRAM into low-power state (identical to power-on reset).
- Perform remaining initialization sequence in Figure 48.
interval.
COREINIT
TC59YM916BKG24A,32A,32B,40B,32C,40C
. Power-on reset circuit in XDR DRAM places XDR DRAM
0
and T
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in the
CALZ
0
Rev 0.1
through the
or