tc59ym916bkg24a ETC-unknow, tc59ym916bkg24a Datasheet - Page 56

• Manufacturer Part Number: tc59ym916bkg24a
• Description: The Second Generation 512-megabit Xdrtm Dram
• Manufacturer: ETC-unknow

DQN15…0
DQN15…0
DQ15…0
DQ15…0
S0[15:0]
[15:0]
S0[15:0]
[15:0]
S0[15:0]
[15:0]
RQ11
RQ11
Multiple Bank Sets and the ERAW Feature
bank set and the odd bank set) according to the least significant bit of the bank address field. This XDR DRAM
supports a feature called “Early Read After Write” (hereafter called “ERAW”).
independently. In addition, each bank set connects to its own internal “S” data bus (called S0 and S1). The receive
interface is able to drive write data onto either of these internal data buses, and the transmit interface is able to
sample read data from either of these internal data buses. These capabilities will permit the delay between a write
column operation and a read column operation to be reduced, thereby improving performance.
included. The write-to-read parameter t
D (a2) and Q (c1).
and read column operations are to the same bank set, but a second parameter t
operations to the opposite bank set. Figure 51 shows how this is possible because there are two internal data buses
S0 and S1. In this example, the four columns read operations are made to the same bank Bb, but they could use
different banks as long as they all belonged to the bank set that was different from the bank set containing Ba (for
the column write operations).
Figure 53. Write/Read Interaction – No ERAW Feature
Figure 54. Write/Read Interaction – ERAW Feature
…RQ0
…RQ0
CFMN
CFMN
Figure 55 shows a block diagram of a XDR DRAM in which the banks are divided into two sets (called the even
The logic that accepts commands on the RQ11…RQ0 signals is capable of operating these two bank sets
Figure 50 shows the timing previously presented in Figure 12, but with the activity on the internal S data bus
When ERAW is supported with odd and even bank sets, the t
CFM
CFM
T
T
WR
WR
a1
a1
0
0
Bb is in different bank set than Ba
T
T
Be is in same bank set as Ba
1
1
T
T
Bank Restrictions
WR
WR
a2
a2
2
2
t ∆WR-D
t CWD
T
T
t CWD
3
3
D(a1)
Transaction a: WR
Transaction c: RD
T
T
RD
4
4
b1
D(a1)
T
T
5
5
D(a2)
t CC
T
T
RD
6
6
b2
t ∆WR
t CAC
t CC
D(a2)
T
T
7
7
∆ WR
DQ gap
Transaction a: WR
Transaction b: RD
T
T
Transaction c: RD
RD
8
8
b3
Q(b1)
ensures that there is adequate turnaround time on the S bus between
a1 = {Ba, Ca1}
D(a1)
c1 = {Bc, Cc1}
T
T
9
9
TC59YM916BKG24A,32A,32B,40B,32C,40C
D(a1)
T
T
RD
10
10
b4
Q(b1)
Q(b2)
D(a2)
T
T
RD
11
11
c1
D(a2)
T
T
DQ gap
12
12
RD
c1
Q(b2)
turnaround
Q(b3)
a1 = {Ba, Ca1}
b1 = {Bb, Cb1}
c1 = {Bc, Cc1}
∆ WR, MIN
T
T
RD
13
turnaround
13
c2
a2 = {Ba, Ca2}
c2 = {Bc, Cc2}
T
T
14
14
t CAC
Q(b3)
Q(b4)
T
T
15
15
parameter must be obeyed when the write
Q(c1)
T
T
16
16
∆ WR-D
Q(c1)
Q(b4)
T
T
17
17
a2 = {Ba, Ca2}
b2 = {Bb, Cb2}
c2 = {Bc, Cc2}
Q(c1)
Q(c2)
T
T
18
18
permits earlier column
Q(c1)
T
T
19
19
2004-12-15 56/76
Q(c2)
T
T
20
20
T
T
t
CC
21
21
B3 = {Bb, Cb3}
T
t
T
t
CC
t
Rev 0.1
CYCLE
CYCLE
22
22
T
T
23
23