tc59ym916bkg24a ETC-unknow, tc59ym916bkg24a Datasheet - Page 60

• Manufacturer Part Number: tc59ym916bkg24a
• Description: The Second Generation 512-megabit Xdrtm Dram
• Manufacturer: ETC-unknow

Timing Conditions
parameters is concerned with parameters for the clock signals. The second section of parameters is concerned with
parameters for the request signals. The third section of parameters is concerned with parameters for the write data
signals. The fourth section of parameters is concerned with parameters for the serial interface signals. The fifth
section is concerned with all other parameters, including those for refresh, calibration, power state transitions, and
initialization
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
N
t
t
t
t
t
t
t
t
t
t
t
CYCLE
CYC,CFM
R, CFM
H, CFM
R, RQ
S, RQ
IR, DQ
S, DQ
DOFF, DQ
CYC, SCK
R, SCK
H, SCK
IR, SI,
S, SI
DLY, SI-RQ
REF
REFA-REFA,AVG
BURST-REFA
COREINIT
CALC
CMD-CALC
CMD-CALZ
CALCE
CALE-CMD
CMD-PDN
PDN-CFM
CFM-PDN
PDN-CMD
Table 13 summarizes all timing conditions that may be applied to the memory component. The first section of
REFA, BURST
or
SYMBOL
, t
, t
, t
, t
, t
t
H, SI
, t
, t
, t
IF, SI
, t
, t
F, RQ
H, RQ
H, DQ
IF, DQ
F, SCK
L, SCK
CALZE
F, CFM
L, CFM
CFM RSL clock - cycle time
CFM/CFMN input - rise and fall time - use minimum for test.
CFM/CFMN input − high and low times
RSL RQ input - rise/fall times (20% - 80%) - use minimum for test.
RSL RQ input to sample
points (set/hold)
DRSL DQ input - rise/fall times (20% - 80%) - use minimum for test.
DRSL DQ input to sample
points (set/hold)
DRSL DQ input delay offset (fixed) to sample points
Serial Interface SCK input - cycle time
Serial Interface SCK input - rise and fall times
Serial Interface SCK input - high and low times
Serial Interface CMD, RST, SDI input - rise and fall times
Serial Interface CMD, SDI input to SCK clock edge - set/hold time
Delay from last SCK clock edge for register write to first CFM edge
with RQ packet. Also, delay from first CFM edge with RQ packet to
the first SCK clock edge for register operation.
Refresh interval. Every row of every bank must be accessed at
least once in this interval with a ROW-ACT, ROWP-REF or
ROWP-REFI command.
Average refresh command interval. ROWP-REFA or ROWP-REFI
commands must be issued at this average rate. This depends upon
t
t
Refresh burst limit. The number of ROWP-REFA or ROWP-REFI
commands which can be issued consecutively at the minimum
command spacing.
Refresh burst interval. The interval between a burst of
N
next ROWP-REFA or ROWP-REFI command.
Interval needed for one initialization after power is applied.
Current calibration interval
Delay between packet with any
command and CALC packet
Delay between CALC/CALZ packet and CALE packet
Delay between CALE packet and packet with any command
Last command before PDN entry
RSL CFM/CFMN stable after PDN entry
RSL CFM/CFMN stable before PDN exit
First command after PDN exit (includes lock time for CFM/CFMN)
REF
REF
REFA,BURST,MAX
/(N
and the number of banks and the number of rows: t
B
*N
R
) = t
REF
ROWP-REFA or ROWP-REFI commands and the
/(2
3
*2
Table 13. Timing Conditions
12
PARAMETER
).
@ 2.500 ns > t
@ 3.333 ns > t
@ 3.830 ns ≥ t
@ 2.500 ns > t
@ 3.333 ns > t
@ 3.830 ns ≥ t
w/ PRE or REFP command
w/ any other command
TC59YM916BKG24A,32A,32B,40B,32C,40C
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
REFI
−4000
−3200
−2400
≥ 2.000 ns
≥ 2.500 ns
≥ 3.333 ns
≥ 2.000 ns
≥ 2.500 ns
≥ 3.333 ns
=
t
REFA-REFA,AVG
0.0625
−0.080
2.000
2.500
3.333
0.080
0.080
0.200
0.020
4096
40%
40%
TBD
TBD
TBD
TBD
MIN
20
10
16
12
24
16
16
16
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5
4
3.830
3.830
3.830
0.200
0.260
0.074
0.080
1.500
MAX
60%
60%
TBD
128
100
5.0
5.0
16
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=488
2004-12-15 60/76
commands
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
UNITS
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
Rev 0.1
Figure (s)
Figure 58
Figure 58
Figure 58
Figure 59
Figure 59
Figure 60
Figure 60
Figure 60
Figure 62
Figure 62
Figure 62
Figure 62
Figure 62
Figure 44
Figure 45
Figure 45
Figure 45
Figure 45
Figure 46
Figure 46
Figure 46
Figure 46
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