tc59ym916bkg24a ETC-unknow, tc59ym916bkg24a Datasheet - Page 24

• Manufacturer Part Number: tc59ym916bkg24a
• Description: The Second Generation 512-megabit Xdrtm Dram
• Manufacturer: ETC-unknow

Read Transactions
the associated data packets) needed to perform a memory access. The state of the memory core and the address of
the memory access determine how many request packets are needed to perform the access.
is already present in the sense amp array for the bank). In addition, the selected row for the memory access
matches the address of the row already sensed (a page hit). This comparison must be done in the memory controller.
In this example, the access is made to row Ra of bank Ba.
(activate or precharge) are needed. A COL packet with RD command to column Ca1 of bank Ba is presented on
edge T
data packets Q (a1) and Q (a2) follow these COL packets after the read data delay t
separated by the column-cycle time t
already open (a row is already present in the sense amp array for the bank). However, the selected row for the
memory access does not match the address of the row already sensed (a page miss). This comparison must be done
in the memory controller. In this example, the access is made to row Ra of bank Ba, and the bank contains a row
other than Ra.
present row (precharge) and access the requested row (activate). A precharge command (PRE to bank Ba) is
presented on edge T
A COL packet with RD command to column Ca1 of bank Ba is presented on edge T
COL packet with RD command to column Ca2 of bank Ba is presented on edge T
and Q(a2) follow these COL packets after the read data delay t
column-cycle time t
already closed (no row is present in the sense amp array for the bank). No row comparison is necessary for this
case; however, the memory controller must still remember that bank Ba has been left closed. In this example, the
access is made to row Ra of bank Ba.
the requested row (activate). An activate command (ACT to row Ra of bank Ba) is presented on edge T
packet with RD command to column Ca1 of bank Ba is presented on edge T
packet with RD command to column Ca2 of bank Ba is presented on edge T
(a2) follow these COL packets after the read data delay t
column-cycle time t
necessary to close the present row (precharge). A precharge command — PRE to bank Ba — is presented on edge
T
the memory controller and its page policy.
previous example except that it uses one read command instead of two read commands. In this case, the core
parameter t
time interval is also constrained by the sum t
constraints (t
length (the number of read commands issued between the activate and precharge commands). In this example, the
t
RAS
10
Figure 10 shows four examples of memory read transactions. A transaction is one or more request packets (and
The first timing diagram shows a page-hit read transaction. In this case, the selected bank is already open (a row
In this case, read data may be directly read from the sense amp array for the bank, and no row operations
The second timing diagram shows an example of a page-miss read transaction. In this case, the selected bank is
In this case, read data may not be directly read from the sense amp array for the bank. It is necessary to close the
The third timing diagram shows an example of a page-empty write transaction. In this case, the selected bank is
In this case, read data may not be directly read from the sense amp array for the bank. It is necessary to access
The fourth timing diagram shows another example of a page-empty read transaction. This is similar to the
The t
a time t
is greater than the sum t
0
RAS
, and a second COL packet with RD command to column Ca2 of bank Ba is presented on edge T
measures the minimum time between an activate command and a precharge command to a bank. This
RDP
RAS
RAS
may also be a constraint upon when the precharge command may be issued.
after the last COL packet with a RD command. Whether the bank is closed or left open depends on
and t
CC
CC
0
. An activate command (ACT to row Ra of bank Ba) is presented on edge T
. This is also the length of each read data packet.
. This is also the length of each read data packet. After the final read command, it may be
RCD-R
+ t
RCD-R
RDP
CC
) will be a function of the memory device’s speed bin and the data transfer
+ t
. This is also the length of each read data packet.
RDP
by the amount ∆t
RCD
TC59YM916BKG24A,32A,32B,40B,32C,40C
−
R
+ t
RDP
CAC
and must be set to whichever is larger. These two
. The two COL packets are separated by the
RDP
CAC
.
. The two COL packets are separated by the
5
7
. Two read data packets Q (a1) and Q
a time t
13
11
. Two read data packets Q(a1)
CAC
RCD-R
a time t
. The two COL packets are
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later. A second COL
RCD-R
6
a time t
later. A second
0
2
Rev 0.1
. A COL
. Two read
RP
later.