tc59ym916bkg24a ETC-unknow, tc59ym916bkg24a Datasheet - Page 57

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tc59ym916bkg24a

Manufacturer Part Number
tc59ym916bkg24a
Description
The Second Generation 512-megabit Xdrtm Dram
Manufacturer
ETC-unknow
Datasheet
Figure 55. XDR DRAM Block Diagram with Bank Sets
Sense Amp 1
Bank 1
Sense Amp Array
16x16*2
Bank Array
Bank (2
Sense Amp (2
16x16*2
S1[15:0] [15:0]
Odd
BA,BR,REFB
3
16x16*2
-1)
6
*2
16x16
6
12
3
-1)
ROW
6
ACT
PRE
R/W
COL
WR odd
Dynamic Width Demux (WR)
ROW
R/W
COL
PRE
ACT
16x16
16x16
Byte Mask (WR)
16x16*2
16x16
1:16 Demux
16
12
1
1
1
1
1
1
6
12
6
D[15:0] [15:0]
6
WR even
DQ15…DQ0
COL logic
6
decode
COL
3
16/t
16
16
TC59YM916BKG24A,32A,32B,40B,32C,40C
CC
RQ11...RQ0
1:2 Demux
PRE logic
decode
12
Reg
PRE
3
DQN15…DQN0
12
ACT logic
decode
Q[15:0] [15:0]
ACT
16
RD odd
Dynamic Width Mux (RD)
3
16:1 mux
16
16x16*2
12
1
1
1
1
6
12
16x16
16x16
6
16x16
ROW
RD even
ACT
PRE
R/W
COL
6
2004-12-15 57/76
ACT
ROW
PRE
R/W
COL
Sense Amp Array
16x16*2
Sense Amp (2
16x16
S0[15:0] [15:0]
16/t
16x16*2
Bank (2
Bank Array
16x16*2
16
CC
Even
Bank (2
6
3
Rev 0.1
-1)
Sense Amp 0
6
*2
3
3
6
-2)
-2)
Bank 0
12

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