tc59ym916bkg24a ETC-unknow, tc59ym916bkg24a Datasheet - Page 30

• Manufacturer Part Number: tc59ym916bkg24a
• Description: The Second Generation 512-megabit Xdrtm Dram
• Manufacturer: ETC-unknow

Propagation Delay
component and the memory controller.
memory component. In this case, the timing will be identical to what has already been shown in the previous
sections; i.e. with all timing measured at the pins of the memory component. This timing diagram was produced by
merging portions of the top and bottom timing diagrams in Figure 12.
read command, followed by a second COL packet with a write command. These accesses all assume a page-hit to an
open bank.
t
between each WR command and the associated write data packet D. There is a read data delay t
RD command and the associated read data packet Q. In this example, all timing parameters have assumed their
minimum values except t
controller and the memory component. This skew is the result of the propagation delay of signal wavefronts on the
wires carrying the signals.
and the CFM/CFMN clock wires between the memory controller and the memory component (the value of t
used here is 1*t
component connected to the RQ wires.
controller and the memory component (the direction in which write data travels, and it is assumed that there is the
same propagation delay t
controller (the direction in which read data travels). The sum of these two propagation delays is also denoted by the
timing parameter t
they are measured at the pins of the memory controller or the pins of the memory component. For example, the
CFM/CFMN signals at the pins of the memory component are t
controller. This is shown by the cycle numbering of the CFM/CFMN signals at the two locations — in this example
cycle T
memory controller in this example. Because the t
propagation delay of the write command, the controller may issue the write data packet D(a0) relative to the COL
packet with the first write command “WR a0” with the normal write data delay t
between the memory controller and memory component were different for the RQ and DQ buses (not shown in this
example), the write data delay at the memory controller would need to be adjusted.
at the memory component relative to the memory controller. The memory component will return the read data
packet Q(b0) relative to this read command with the normal read data delay t
component).
component back to the memory controller. The effective read data delay measured between the read command and
the read data at the memory controller will be t
controller to memory component. The t
they travel from memory component to memory controller.
∆ RW
Figure 13 shows two timing diagrams that display the system-level timing relationships between the memory
The timing diagram at the top of the figure shows the case of a write-read-write command and data at the
The example shown is that of a single COL packet with a write command, followed by a single COL packet with a
A timing interval t
The lower timing diagram in the figure shows the case where timing skew is present between the memory
The example in the lower diagram assumes that there is a propagation delay of t
In addition, it is assumed that there is a propagation delay t
As a result of these propagation delays, the position of packets will have timing skews that depend upon whether
All the request packets on the RQ wires will have a t
A propagation delay is seen by the read command — that is, the read command will be delayed by a t
The read data packet will be skewed by an additional propagation delay of t
The t
is required between the RD command and the second WR command. There is a write data delay t
1
PD − RQ
at the memory controller aligns with cycle T
factor is caused by the propagation delay of the request packets as they travel from memory
CYCLE
PD,CYC
∆ WR
). Note that in an actual system the t
WR − BUB,XDR DRAM
PD − Q
is required between the first WR command and the RD command, and a timing interval
= t
PD − D
along the DQ/DQN wires between the memory component and the memory
+ t
PD − Q
PD − Q
.
factor is caused by the propagation delay of the read data packets as
.
CAC
TC59YM916BKG24A,32A,32B,40B,32C,40C
PD − D
+ t
0
at the memory component.
PD − RQ
PD − RQ
propagation delay of write data matches the t
PD − RQ
+ t
PD − D
skew at the memory component relative to the
PD − RQ
PD − Q
value will be different for each memory
along the DQ/DQN wires between the memory
.
later than at the pins of the memory
CAC
PD − Q
CWD
(at the pins of the memory
PD − RQ
as it travels from the memory
. If the propagation delays
along both the RQ wires
2004-12-15 30/76
CAC
PD − RQ
between the
Rev 0.1
CWD
PD − RQ
PD − RQ
skew