tc59ym916bkg24a ETC-unknow, tc59ym916bkg24a Datasheet - Page 26

• Manufacturer Part Number: tc59ym916bkg24a
• Description: The Second Generation 512-megabit Xdrtm Dram
• Manufacturer: ETC-unknow

Interleaved Transactions
another; a transaction is started before an earlier one is completed.
page-empty access; that is, a bank is in a closed state prior to an access, and is precharged after the access. With
this assumption, each transaction requires the same number of request packets at the same relative positions. If
banks were allowed to be in an open state, then each transaction would require a different number of request
packets depending upon whether the transaction was page-empty, page-hit, or page-miss. This situation is more
complicated for the memory controller, and will not be analyzed in this document.
left side of the timing diagram. The first three show the timing slots used by each of the three requests packet types
(ACT, COL and PRE), and the fourth set (ALL) shows the previous three merged together. This allows the pattern
used for allocating request slots for the different packets to be seen more clearly.
the t
because each bank address — Ba, Bb, Bc, Bd, and Be — is assumed to be different from another. If two of the bank
addresses are the same, the later transaction would need to wait until the earlier transaction had completed its
precharge operation. Five different banks are needed because the effective t
packet spacing is determined by the t
access. The phasing of the COL packet spacing is determined by the t
required the COL packets to occupy the same request slots as the ROWA packets (this case is not shown), the
DELC field in the COL packet could be used to place the COL packet one t
write data packets are written to a bank in each transaction. The DQ bus is completely filled with write data; no
idle cycles need to be introduced because there are no resource conflicts in this example.
spacing is determined by the t
parameter. If the value of t
packets already assigned (this case is not shown), the delay field in the ROWP packet could be used to place the
ROWP packet one or more t
of request pins RQ11…RQ0 shown along the left side of the timing diagram, allowing the pattern used for
allocating request slots for the different packets to be seen more clearly.
the t
because each bank address — Ba, Bb, Bc, and Bd — is assumed to be different from another. Four different banks
are needed because the effective t
spacing is determined by the t
phasing of the COL packet spacing is determined by the t
COL packets to occupy the same request slots as the ROWA packets (this case is not shown), the DELC field in the
COL packet could be used to place the packet one t
read data packets are read from a bank in each transaction. The DQ bus is completely filled with read data — that
is, no idle cycles need to be introduced because there are no resource conflicts in this example.
ROWP packet spacing is determined by the t
by the t
ROWA or COL packets already assigned (this case is not shown), the delay field in the ROWP packet could be used
to place the ROWP packet one or more t
Figure 11 shows two examples of interleaved transactions. Interleaved transactions are overlapped with one
The timing diagram at the top of the figure shows interleaved write transactions. Each transaction assumes a
In the interleaved page−empty write example, there are four sets of request pins RQ11…RQ0 shown along the
The slots at {T
The slots at {T
The DQ bus slots at {T
The slots at {T
There is an example of an interleaved page-empty read at the bottom of the figure. As before, there are four sets
The slots at {T
The slots at {T
The DQ bus slots at {T
The slots at {T
RR
RR
RDP
parameter. There should not be interference between the interleaved transactions due to resource conflicts
parameter. There should not be interference between the interleaved transactions due to resource conflicts
parameter. If the value of t
0
1
14
0
5
10
, T
, T
, T
, T
, T
, T
4
3
4
7
, T
, T
18
, T
, T
14
, T
, T
8
5
8
9
7
11
, T
, T
, T
, T
, T
22
18
, T
WRP
12
7
12
11
CYCLE
, ...} are used for ROWP packets with PRE commands. This frequency of ROWP packet
, T
9
, T
, T
13
, ...} are used for ROWA packets with ACT commands. This spacing is determined by
, ...} are used for ROWA packets with ACT commands. This spacing is determined by
, ...} are used for COL packets with RD commands. This frequency of the COL packet
PP
CC
22
9
, T
11
, T
required the ROWP packets to occupy the same request slots as the ROWA or COL
, ...} are used for ROWP packets with PRE commands. This frequency of the
parameter. The phasing of the ROWP packet spacing is determined by the t
RC
parameter and by the fact that there are two column accesses per row access. The
, T
15
11
earlier.
, T
13
is 16 × t
, ...} are used for COL packets with WR commands. This frequency of the COL
CC
, ...} carry the write data packets { D (a1), D (a2), D (b1), D (b2), .... }. Two
17
RDP
CYCLE
parameter and by the fact that there are two column accesses per row
, ...} carry the read data packets { Q (a1), Q (a2), Q (b1), Q (b2), ...}. Two
required the ROWP packets to occupy the same request slots as the
CYCLE
PP
earlier.
parameter. The phasing of the ROWP packet spacing is determined
TC59YM916BKG24A,32A,32B,40B,32C,40C
CYCLE
.
RCD
earlier.
−
R
parameter. If the value of t
RCD-W
CYCLE
RC
parameter. If the value of t
(t
RC
earlier.
+ ∆t
RC
) is 20 × t
2004-12-15 26/76
RCD
−
R
required the
CYCLE
Rev 0.1
RCD-W
.
WRP