tc59ym916bkg24a ETC-unknow, tc59ym916bkg24a Datasheet - Page 66

• Manufacturer Part Number: tc59ym916bkg24a
• Description: The Second Generation 512-megabit Xdrtm Dram
• Manufacturer: ETC-unknow

CFMN
RSL RQ Receive Timing
represents a magnified view of the pins and only a few clock cycles (CFM and CFMN are the clock signals). Timing
events are measured to and from the primary CFM/CFMN crossing point in which CFM makes its
high-voltage-to-low-voltage transition. The RQ11…RQ0 signals are low true: a high voltage represents a logical
zero and a low voltage represents a logical one. Timing events on the RQ11…RQ0 pins are measured to and from
the point that the signal reaches the level of the reference voltage V
The rise (t
levels.
time, t
“1”) has a set time (t
CFM/CFMN crossing point.
Figure 58. RSL RQ Receive Waveform
RQ11
CFM
RQ0
Figure 58 shows a timing diagram for the RQ11…RQ0 request pins of the memory component. This diagram
Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals.
There are two data receiving windows defined for each RQ11…RQ0 signal. The first of these (labeled “0”) has a set
S,RQ
20% = V
80% = V
R,RQ
, and a hold time, t
IL,RQ
IL,RQ
) and fall time (t
S,RQ
+ 0.2*(V
+ 0.8*(V
) and a hold time (t
IH,RQ
IH,RQ
H,RQ
F,RQ
t
CYCLE
−V
−V
, measured around the primary CFM/CFMN crossing point. The second (labeled
) of the signals are measured from the 20% and 80% points of the full-swing
IL,RQ
IL,RQ
)
)
H,RQ
t
t
TC59YM916BKG24A,32A,32B,40B,32C,40C
) measured around a point 0.5 × t
R,RQ
R,RQ
t
t
S,RQ
S,RQ
0
0
t
t
H,RQ
H,RQ
t
t
F,RQ
F,RQ
REF, RSL
[1/2]*t
[1/2]*t
CYCLE
CYCLE
.
t
t
S,RQ
S,RQ
CYCLE
1
1
t
t
H,RQ
H,RQ
after the primary
2004-12-15 66/76
Rev 0.1
Logic 0
V
80%
V
20%
V
Logic 1
Logic 0
V
80%
V
20%
V
Logic 1
IH,RQ
REF,RSL
IL,RQ
IH,RQ
REF,RSL
IL,RQ