tc59ym916bkg24a ETC-unknow, tc59ym916bkg24a Datasheet - Page 28

• Manufacturer Part Number: tc59ym916bkg24a
• Description: The Second Generation 512-megabit Xdrtm Dram
• Manufacturer: ETC-unknow

Read/Write Interaction
section will describe the interaction of read and write transactions and the spacing required to avoid channel and
core resource conflicts.
COL packets with WR commands are presented on cycles T
t
before a COL packet with a RD command may be presented. Two COL packets with RD commands are presented
on cycles T
is required for turning around internal bi-directional interconnections (inside the device). This time must be
observed regardless of whether the write and read commands are directed to the same bank or different banks. A
gap t
Q (b1) packet (measured at the appropriate packet reference points). The size of this gap can be evaluated by
calculating the difference between cycles T
MIN
by a write transaction. Two COL packets with RD commands are presented on cycles T
packets are returned a time t
packet with a RD command before a COL packet with a WR command may be presented. Two COL packets with
WR commands are presented on cycles T
cycles T
(outside the device). This time must be observed regardless whether the read and write commands are directed to
the same bank or different banks. The time t
calculating the difference between cycles T
values.
CWD
The previous section described overlapped read transactions and overlapped write transactions in isolation. This
Figure 12 shows a timing diagram (top) for the first case, a write transaction followed by a read transaction. Two
In the second case, the timing diagram displayed at the bottom of Figure 12 illustrates a read transaction followed
or
In this example, the value of t
In this example, the values of t
. The values of t
WR
t
t
t
later on cycles T
WR
∆ RW
∆ RW
13
−
BUB, XDR DRAM
−
BUB,XDRDRAM
and T
11
+ t
= (t
and T
CWD
CAC
15
. The time t
13
= t
− t
∆ WR
. The read data packets are returned a time t
CAC
CWD
4
and T
and t
will appear on the DQ bus between the end of the D (a2) packet and the beginning of the
= t
+ t
) + t
∆ WR
CAC
CC
6
∆ RW
CAC
. The device requires a time t
CC
WR-BUB, XDR DRAM
+ t
∆ RW
later on cycles T
+ t
+ t
are equal to their minimum values.
is required for turning around the external DQ bi-directional interconnections
RW
CAC
RW
, t
−
CAC
BUB,XDRDRAM
−
10
BUB,XDRDRAM
− t
2
2
and T
, t
CWD
and T
and T
∆ RW
CWD
TC59YM916BKG24A,32A,32B,40B,32C,40C
12
− t
depends upon four timing parameters, and may be evaluated by
17
6
13
, t
. The write data packets are presented a time t
and T
CC
using the two timing paths:
using the two timing paths:
CC
is greater than its minimum value of t
, and t
8
. The device requires a time t
0
∆ WR
and T
RW
after the second COL packet with a WR command
−
BUB,XDR DRAM
CAC
2
. The write data packets are presented a time
later on cycles T
are equal to their minimum
0
17
∆ RW
and T
and T
2004-12-15 28/76
WR
after the second COL
−
2
BUB, XDR DRAM,
. The read data
19
. The time t
CWD
Rev 0.1
later on
∆ WR