tc59ym916bkg24a ETC-unknow, tc59ym916bkg24a Datasheet - Page 65

• Manufacturer Part Number: tc59ym916bkg24a
• Description: The Second Generation 512-megabit Xdrtm Dram
• Manufacturer: ETC-unknow

Receive/Transmit Timing
Clocking
represents a magnified view of these pins. This diagram shows only one clock cycle.
signals — a low voltage represents a logical zero and a high voltage represents a logical one. There are two crossing
points in each clock cycle. The primary crossing point includes the high−voltage−to−low−voltage transition of CFM
(indicated with the arrowhead in the diagram). The secondary crossing point includes the
low−voltage−to−high−voltage transition of CFM. All timing events on the RSL signals are referenced to the first set
of edges.
this is how the clock-cycle time (t
measured.
The rise (t
levels.
Figure 57. Clocking Waveforms
CFMN
Figure 57 shows a timing diagram for the CFM/CFMN clock pins of the memory component. This diagram
CFM and CFMN are differential signals: one signal is the complement of the other. They are also high-true
Timing events are measured to and from the crossing point of the CFM and CFMN signals. In the timing diagram,
Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals.
CFM
20% = V
80% = V
R,CFM
IL,CFM
IL,CFM
) and fall time (t
+ 0.2*(V
+ 0.8*(V
IH,CFM
IH, CFM
t
L,CFM
CYCLE
F,CFM
t
−V
CYCLE
−V
) of the signals are measured from the 20% and 80% points of the full-swing
or t
IL,CFM
IL,CFM
t
CYC,CFM
R,CFM
or t
CYC,CFM
)
)
TC59YM916BKG24A,32A,32B,40B,32C,40C
), clock-low time (t
t
H,CFM
L,CFM
t
F,CFM
) and clock-high time (t
2004-12-15 65/76
H,CFM
Rev 0.1
Logic 1
V
80%
20%
V
Logic 0
) are
IH,CFM
IL,CFM