tc59ym916bkg24a ETC-unknow, tc59ym916bkg24a Datasheet - Page 33

• Manufacturer Part Number: tc59ym916bkg24a
• Description: The Second Generation 512-megabit Xdrtm Dram
• Manufacturer: ETC-unknow

Register Operations
Serial Transactions
signaling levels. The other four pins use RSL signaling levels. RST, CMD, SDI, and SDO use a timing window,
which surrounds the falling edge of SCK). The RST pin is used for initialization.
transaction starts on cycle S
does not need to be asserted if there is no transaction.
Serial Write Transaction
the CMD pin. This indicates to the XDR DRAM that the remaining 28 bits constitute a serial transaction.
serial device write transaction.
accessed.
accessed.
control register.
and all devices perform the register write. The SDI and SDO pins are not used during either serial write
transaction.
Serial Read Transaction
CMD pin. This indicates that the remaining 28 bits constitute a serial transaction.
a serial device read transaction.
accessed.
on the SDO output driver.
are the SRD [7:0] field. This is the read data that is accessed from the selected control register. Note the output
timing convention here: bit SRD [7] is driven from a time t
S
devices perform the register read. This is used for device testing.
field doesn’t match the SID [5:0] field of the transaction. Instead of driving read data from an internal register for
cycle edges S
output pin during this same period.
SCMD [1:0]
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The serial interface consists of five pins. This includes RST, SCK, CMD, SDI, and SDO. SDO uses CMOS
Figure 14 and Figure 15 show examples of a serial write transaction and a serial read transaction. Each
The serial device write transaction in Figure 14 begins with the Start [3:0] field. This consists of bits “1100” on
The next two bits are the SCMD [1:0] field. This field contains the serial command, the bits 00 in the case of a
The next eight bits are “00” and the SID [5:0] field. This field contains the serial identification of the device being
The next eight bits are the SADR [7:0] field. This field contains the serial address of the control register being
A single bit “0” follows next. This bit allows one cycle for the access time to the control register.
The next eight bits on the CMD pin is the SWD [7:0] field. This is the write data that is placed into the selected
A final bit “0” is driven on the CMD pin to finish the serial write transaction.
A serial broadcast write is identical except that the contents of the SID [5:0] field in the transaction is ignored
The serial device read transaction in Figure 15 begins with the Start [3:0] field. This consists of bits “1100” on the
The next two bits are the SCMD [1:0] field. This field contains the serial command, and the bits “10” in the case of
The next eight bits are “00” and the SID [5:0] field. This field contains the serial identification of the device being
The next eight bits are the SADR [7:0] field and contain the serial address of the control register being accessed.
A single bit “0” follows next. This bit allows one cycle for the access time to the control register and time to turn
The next eight bits on the CMD pin are the sequence “00000000”. At the same time, the eight bits on the SDO pin
A final bit “0” is driven on the CMD pin to finish the serial read transaction.
A serial forced read is identical except that the contents of the SID [5:0] field in the transaction is ignored and all
Figure 16 shows the response of a DRAM to a serial device read transaction when its internal SID [5:0] register
. The bit is sampled in the controller by the edge S
00
01
10
11
Command
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SDW
SBW
SDR
SFR
through S
Serial device write-one device is written, the one whose SID[5:0] register matches the SID [5:0] filed of the
transaction.
Serial broadcast write – all devices are written, regardless of the contents of the SID [5:0] register and the
SID [5:0] transaction field.
Serial device read – one device is read, the one whose SID[5:0] register matches the SID [5:0] field of the
transaction.
Serial forced read – all devices are read, regardless of the contents of the SID [5:0] register and the SID
[5:0] transaction field.
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4
on the SDO output pin, it passes the input data from the SDI input pin to the SDO
and requires 32 SCK edges. The next serial transaction can begin on cycle S
Table 8. SCMD Field Encoding Summary
TC59YM916BKG24A,32A,32B,40B,32C,40C
27
.
Q, SI, MAX
DESCRIPTION
after edge S
26
to a time t
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Q, SI, MIN
Rev 0.1
after edge
36
. SCK