tc59ym916bkg24a ETC-unknow, tc59ym916bkg24a Datasheet - Page 55

• Manufacturer Part Number: tc59ym916bkg24a
• Description: The Second Generation 512-megabit Xdrtm Dram
• Manufacturer: ETC-unknow

DQN15…0
DQ15…0
RQ11
…RQ0
CFMN
bus that is used in the example in Figure 51.
two successive WR commands in COL packets. The one difference is that the COLM packet includes a M [7:0] field
that indicates the reserved bit pattern (for the eight bits of each byte) that indicates that the byte is not to be
written. This requires that the alignment of bytes within the data packet be defined, and also that the bit
numbering within each byte be defined (note that this was not necessary for the unmasked WR command). In the
figure, bytes are contained within a single DQ/DQN pin pair - this is necessary so the dynamic width feature can be
supported. Thus, each pin pair carries two bytes of each data packet. Byte [0] is transferred earlier than byte [1],
and bit [0] of each byte (corresponding to M [0]) is transferred first, followed by the remaining bits in succession).
Figure 52. Write-Masked (WRM) Transaction Example
CFM
Note that other systems might use a data transfer size that is different than the 64 bytes per t
Figure 52 shows the timing of two successive WRM commands in COLM packets. The timing is identical to that of
WRM
T
Bit-and Byte-numbering
convention for write
and read data packets.
DQN15
0
a1
DQN0
DQN1
DQ15
DQ0
DQ1
t
CC
T
t
1
CWD
WRM
T
2
a2
[0]
[0]
[0]
T
3
D(a1)
[1]
[1]
[1]
T
4
T
[2]
[2]
[2]
5
D(a2)
T
6
Byte [15]
[3]
[3]
[3]
Byte [0]
Byte [1]
T
7
[4]
[4]
[4]
T
8
T
[5]
[5]
[5]
9
TC59YM916BKG24A,32A,32B,40B,32C,40C
T
RD
10
a1
[6]
[6]
[6]
T
11
[7]
[7]
[7]
T
12
t
CAC
T
[8]
[8]
[8]
13
T
14
[9]
[9]
[9]
T
15
[10]
[10]
[10]
T
16
Q(a1)
T
Byte [16+0]
Byte [16+1]
[11]
[11]
Byte [16+15]
[11]
17
T
18
[12]
[12]
[12]
T
19
2004-12-15 55/76
[13]
[13]
[13]
T
20
CC
T
[14]
[14]
[14]
21
interval per RQ
T
t
CYCLE
22
[15]
[15]
[15]
Rev 0.1
T
23