tc59ym916bkg24a ETC-unknow, tc59ym916bkg24a Datasheet - Page 42

• Manufacturer Part Number: tc59ym916bkg24a
• Description: The Second Generation 512-megabit Xdrtm Dram
• Manufacturer: ETC-unknow

Maintenance Operations
Refresh Transactions
a single refresh operation. Bank Ba is assumed to be closed (in a precharged state) when a REFA command is
received in a ROWP packet on clock edge T
(REFH/REFM/REFL) to be opened (sensed) and placed in the sense amp array for the bank.
address and delay value, and both cause the selected bank to open (to become sensed.) The difference is that the
ACT command is accompanied by a row address in the ROWA packet, while the REFA and REFI commands use a
row address in the REFr register (REFH/REFM/REFL).
closed (precharged), leaving the bank in the same state as when the refresh transaction began.
delay value, and both cause the selected bank to close (to become precharged).
same in this example). This starts a second refresh cycle. Each refresh transaction requires a total time t
+ t
packet with a REFA command in the top timing diagram.
Interleaved Refresh Transactions
maintenance in a real system.
presented starting at edge T
addressed to a different bank (Ba through Bh) but uses the same row address from the REFr (REFH/REFM/REFL)
register. The eighth REFI command uses this address and then increments it so the next set of eight REFA/REFI
commands will refresh the next set of rows in each bank.
the first ROWP packet with a REFA command). The packets are spaced with intervals of t
commands, each REFP command is addressed to a different bank (Ba through Bh).
transactions may be interleaved with the refresh transactions before and after the burst to prevent any loss of bus
efficiency. In other words, a ROWA packet with ACT command for a read or write could have been presented at
edge T–
command for a read or write could have been presented at edge T
starts at edge T
precharge commands and the read or write commands) could be slotted in among the request packets for the
refresh transactions.
Figure 44 contains two timing diagrams showing examples of refresh transactions. The top timing diagram shows
Note that the REFA and REFI commands are similar to the ACT command functionally; both specify a bank
After a time t
Note that the REFP command is equivalent to the PRE command functionally; both specify a bank address and
After a time t
Each row of each bank must be refreshed once in every t
The lower timing diagram in Figure 44 represents one way a memory controller might handle refresh
A series of eight ROWP packets with REFA commands (except for the last which is a REFI command) are
A series of eight ROWP packets with REFP commands are presented effectively at edge T
This burst of eight refresh transactions fully utilizes the memory component. However, other read and writes
RP
, but refresh transactions to different banks may be interleaved like normal read and write transactions.
4
(a time t
RAS
RP
32
RR
). In both cases, the other request packets for the interleaved read or write accesses (the
, another ROWP packet with REFA command to bank Bb is presented (banks Ba and Bb are the
, a ROWP packet with REFP command to bank Ba is presented. This causes the bank to be
before the first refresh transaction starts at edge T
0
.
The packets are spaced with intervals of t
0
. The REFA command causes the row addressed by the REFr register
TC59YM916BKG24A,32A,32B,40B,32C,40C
REF
interval. This is shown with the fourth ROWP
36
(a time t
RR
0
). Also, a ROWA packet with ACT
. Each REFA or REFI command is
RR
after the last refresh transaction
PP
2004-12-15 42/76
10
. Like the REFA/REFI
(a time t
RAS
Rev 0.1
RC
after
= t
RAS