tc59ym916bkg24a ETC-unknow, tc59ym916bkg24a Datasheet - Page 67

• Manufacturer Part Number: tc59ym916bkg24a
• Description: The Second Generation 512-megabit Xdrtm Dram
• Manufacturer: ETC-unknow

DRSL DQ Receive Timing
This diagram represents a magnified view of the pins and shows only a few clock cycles are shown (CFM and
CFMN are the clock signals). Timing events are measured to and from the primary CFM/CFMN crossing point in
which CFM makes its high−voltage−to−low−voltage transition. The DQ15…DQ0/DQN15…DQN0 signals are
high-true: a low voltage represents a logical zero and a high voltage represents a logical one. They are also
differential—timing events on the DQ15…DQ0/DQN15...DQN0 pins are measured to and from the point that each
differential pair crosses.
The rise time (t
full-swing levels.
windows for a particular DQi/DQNi pin pair is referenced to an offset parameter t
on the values {0, 1, ..15} and refers to each of the DQ15…DQ0/DQN15…DQN0 pin pairs).
point for the DQi/DQNi pin pair. The 16 receiving windows are placed at times t
index “j” may take on the values {1, 2, ..16} and refers to each of the receiving windows for the DQi/DQNi pin pair).
to lie inside the range {t
change during system operation. Its value can be determined at initialization.
set time (t
CFM/CFMN crossing point.
Each window has a set time (t
after the primary CFM/CFMN crossing point.
Figure 59 shows a timing diagram for receiving write data on the DQ/DQN data pins of the memory component.
Because timing intervals are measured in this fashion, it is necessary to constrain the slew rate of the signals.
There are 16 data receiving windows defined for each DQ15…DQ0/DQN15…DQN0 pin pair. The receiving
The t
The offset values t
The 16 receiving windows (j = 1…16) for the first pair DQ0/DQN0 are labeled “1” through “16”. Each window has a
The 16 receiving windows (j = 1…16) for the each of the other pairs DQi/DQNi are also labeled “1” through “16”.
DOFF,DQi
20% = V
80% = V
S,DQ
) and a hold time (t
IL,DQ
IL,DQ
IR,DQ
parameter determines the time between the primary CFM/CFMN crossing point and the offset
DOFF,DQi
) and fall time (t
+ 0.2 × (V
+ 0.8 × (V
DOFF,MIN
for each of the 16 DQi/DQNi pin pairs can be different. However, each is constrained
S,DQ
IH,DQ
IH,DQ
H,DQ
,
) and a hold time (t
t
DOFF,MAX
−V
−V
IF,DQ
) measured around a point t
IL,DQ
IL,DQ
) of the signals are measured from the 20% and 80% points of the
)
)
}. Furthermore, each offset value t
TC59YM916BKG24A,32A,32B,40B,32C,40C
H,DQ
) measured around a point t
DOFF,DQ0
+ (j/8) × t
DOFF,DQi
DOFF,DQi
DOFF,DQi
CYCLE
DOFF,DQi
+ (j/8) × t
is static and will not
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(the index “i” may take
after the primary
+ (j/8) × t
CYCLE
Rev 0.1
CYCLE
(the