r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 84

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 6.7
6.3.5
6.3.6
6.3.7
6.3.8
When the RIS bit in the RISR register is 1 (watchdog timer reset enabled), if the watchdog timer underflows,
the CPU, SFRs, and I/O ports are initialized. Next, the program located at the address indicated by the reset
vector is executed. The low-speed on-chip oscillator clock with no division is automatically selected as the CPU
clock after a reset.
For the states of the SFR after a watchdog timer reset, refer to 3.2 Special Function Registers (SFRs).
The internal RAM is not initialized. When the watchdog timer underflows while writing to the internal RAM,
the RAM values will be undefined.
The underflow period and refresh acceptance period for the watchdog timer are set by bits WDTUFS0 and
WDTUFS1 and bits WDTRCS0 and WDTRCS1 in the OFS2 register, respectively.
For details on the watchdog timer, refer to 8. Watchdog Timer.
When the PM03 bit in the PM0 register is 1 (MCU reset), the CPU, SFRs, and I/O ports are initialized. Next, the
program located at the address indicated by the reset vector is executed. The low-speed on-chip oscillator clock
with no division is automatically selected as the CPU clock after a reset.
For the states of the SFRs after a software reset, refer to 3.2 Special Function Registers (SFRs).
The internal RAM is not initialized.
The CWR bit in the RSTFR register is used to determine whether a cold start-up reset process was initiated at
power-on, or whether a warm start-up reset process was initiated during operation.
The CWR bit is set to 0 (cold start-up) at power-on and also set to 0 by a voltage monitor 0 reset. If 1 is written
to the CWR bit by a program, it is set to 1. This bit remains unchanged after a hardware reset, software reset, or
watchdog timer reset.
The cold start-up/warm stat-up determination function uses the voltage monitor 0 reset.
Figure 6.7 shows an Example of Cold Start-Up/Warm Start-Up Function Operation.
The RSTFR register can be used to detect whether a hardware reset, software reset, or watchdog timer reset has
occurred.
If a hardware reset occurs, the HWR bit in the RSTFR register is set to 1 (detected). If a software reset occurs,
the SWR bit in the RSTFR register is set to 1 (detected). If a watchdog timer reset occurs, the WDR bit in the
RSTFR register is set to 1 (detected).
Watchdog Timer Reset
Software Reset
Cold Start-Up/Warm Start-Up Determination Function
Reset Source Determination Function
Preliminary document
Specifications in this document are tentative and subject to change.
Example of Cold Start-Up/Warm Start-Up Function Operation
CWR bit in RSTFR register
Voltage monitor 0 reset
VCC
Vdet0
5 V
0 V
Set to 1 by a
program
Set to 1 by a
program
Page 53 of 725
6. Resets