r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 105

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
8.2.1
Notes:
8.2.2
Note:
b7 to b0
UFIF Bit (WDT underflow detection flag)
After Reset
After Reset
After Reset
1. Do not write 0 to the UFIF bit after it is set to 1. After reading this bit as 1, wait for at least one cycle of the count
2. The RIS bit is set to 1 by writing 1 by a program, but writing 0 to this bit has no effect.
1. Only write to the WDTR register while the watchdog timer is counting.
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
Address 00020h
Address 00021h
source before writing 0 to it.
When the CSPRO bit in the CSPR register is 1 (count source protection mode enabled), the RIS bit is
automatically set to 1.
Set the PRC1 bit in the PRCR register to 1 (write enabled) before rewriting the RISR register.
[Condition for setting to 0]
• When 0 is written to this bit.
[Conditions for setting to 1]
• When the watchdog timer underflows while the RIS bit is 0 (watchdog timer interrupt).
• When a refresh is executed during a period other than the acceptance period (illegal refresh) while the RIS bit
Symbol
Symbol
is 0 (watchdog timer interrupt).
Symbol
Bit
Bit
UFIF
RIS
Reset Interrupt Select Register (RISR)
Watchdog Timer Reset Register (WDTR)
—
—
—
—
—
—
The watchdog timer is initialized by writing 00h and then FFh during the acceptance period.
The initial value of the watchdog timer is specified by bits WDTUFS0 and WDTUFS1 in the OFS2
register.
The above applies when the CSPROINI bit in the OFS register is 0.
The above applies when the CSPROINI bit in the OFS register is 1.
Preliminary document
Specifications in this document are tentative and subject to change.
RIS
b7
b7
—
1
0
1
Nothing is assigned. The write value must be 0. The read value is 0.
WDT underflow detection flag
WDT interrupt/reset switch bit
(1)
UFIF
b6
b6
—
0
0
1
Bit Name
b5
b5
—
—
0
0
1
b4
b4
—
—
0
0
1
Function
0: No watchdog timer underflow
1: Watchdog timer underflow
0: Watchdog timer interrupt
1: Watchdog timer reset
b3
b3
—
—
0
0
1
b2
b2
—
—
0
0
1
Function
b1
b1
—
—
(2)
0
0
1
(1)
b0
—
b0
—
0
0
1
8. Watchdog Timer
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R/W
R/W
R/W
R/W
—
W