r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 461

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
20.3.3.4
20.3.3.5
20.3.3.6
20.3.3.7
The data written to bits b0 to b7 (D0 to D7) in the U2TB register is output in descending order from D7.
The 9th bit (D8) is ACK or NACK.
Set the initial value of SDA2 transmit output when the IICM bit is set to 1 (I
in the U2MR register are set to 000b (serial interface disabled).
Bits DL0 to DL2 in the U2SMR3 register allow addition of no delays or a delay of two to eight cycles of the
U2BRG count source clock to the SDA2 output.
Setting the SDHI bit in the U2SMR2 register to 1 (SDA2 output disabled) forcibly sets the SDA2 pin to the
high-impedance state. Do not write to the SDHI bit at the rising edge of the UART2 transfer clock.
When the IICM2 bit in the U2SMR2 register is set to 0, the 1st to 8th bits (D0 to D7) of received data are stored
in bits b0 to b7 in the U2RB register. The 9th bit (D8) is ACK or NACK.
When the IICM2 bit is set to 1, the 1st to 7th bits (D1 to D7) of received data are stored in bits b0 to b6 in the
U2RB register and the 8th bit (D0) is stored in bit b8 in the U2RB register. Even when the IICM2 bit is set to 1,
if the CKPH bit in the U2SMR3 register is 1 (with clock delay), the same data as when the IICM2 bit is 0 can be
read by reading the U2RB register after the rising edge of 9th bit of the clock.
If the STSPSEL bit in the U2SMR4 register is set to 0 (start and stop conditions not output) and the ACKC bit
in the U2SMR4 register is set to 1 (ACK data output), the value of the ACKD bit in the U2SMR4 register is
output from the SDA2 pin.
If the IICM2 bit is set to 0, a NACK interrupt request is generated if the SDA2 pin remains high at the rising
edge of the 9th bit of the transmit clock. An ACK interrupt request is generated if the SDA2 pin is low at the
rising edge of the 9th bit of the transmit clock.
If ACK2 (UART2 reception) is selected to generate a DTC request source, a DTC transfer can be activated by
detection of an acknowledge.
If a start condition is detected while the STAC bit is set to 1 (UART2 initialization enabled), the serial interface
operates as described below.
• The transmit shift register is initialized, and the contents of the U2TB register are transferred to the transmit
• The receive shift register is initialized, and the serial interface starts receiving data when the next clock pulse
• The SWC bit is set to 1 (SCL wait output enabled). Consequently, the SCL2 pin is pulled low at the falling
Note that when UART2 transmission/reception is started using this function, the TI bit does not change state.
Select the external clock as the transfer clock to start UART2 transmission/reception with this setting.
shift register. In this way, the serial interface starts sending data when the next clock pulse is applied.
However, the UART2 output value does not change state and remains the same as when a start condition was
detected until the first bit of data is output in synchronization with the input clock.
is applied.
edge of the 9th clock pulse.
Preliminary document
Specifications in this document are tentative and subject to change.
SDA Output
SDA Input
ACK and NACK
Initialization of Transmission/Reception
2
C mode) and bits SMD2 to SMD0
20. Serial Interface (UART2)
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