r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 211

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
13.3.10 DTC Activation Source Acknowledgement and Interrupt Source Flags
13.3.10.1 Interrupt Sources Except for Clock Synchronous Serial Interface
13.3.10.2 Flash Memory
13.3.10.3 SSU/I
13.3.10.4 SSU/I
When the DTC activation source is an interrupt source except for the SSU/I
transfer is started by the interrupt source, the same DTC activation source cannot be acknowledged for 8 to 12
cycles of the CPU clock. If a DTC activation source is generated during DTC operation and acknowledged, the
same DTC activation source cannot be acknowledged for 8 to 12 cycles of the CPU clock on completion of the
DTC transfer immediately before the DTC is activated by the source.
When the DTC activation source is flash memory ready status, even if a flash memory ready status interrupt
request is generated, it is not acknowledged as the DTC activation source after the RDYSTI bit in the FST
register is set to 1 (flash ready status interrupt requested) and before the DTC sets the RDYSTI bit to 0 (no flash
ready status interrupt requested). If a flash memory ready status interrupt request is generated after the DTC sets
the RDYSTI bit to 0, the DTC acknowledges it as the activation source. 8 to 12 cycles of the CPU clock are
required after the DTC starts transfer when the RDYSTI bit is set to 1 and before the DTC sets the interrupt
request flag to 0.
When the DTC activation source is SSU/I
The RDRF bit in the SISR register is set to 0 (no data in SIRDR register) by reading the SIRDR register. If an
interrupt source for receive data full is subsequently generated, the DTC acknowledges it as the activation
source.
When the DTC activation source is SSU/I
transfer. The TDRE bit in the SISR register is set to 0 (data is not transferred from registers SITDR to SIDR) by
writing to the SITDR register. If an interrupt source for transmit data empty is subsequently generated, the DTC
acknowledges it as the activation source.
Preliminary document
Specifications in this document are tentative and subject to change.
(SSU/I
2
2
2
C bus Receive Data Full
C bus Transmit Data Empty
C) and Flash Memory
2
2
C bus receive data full, read the SIRDR register using a data transfer.
C bus transmit data empty, write to the SITDR register using a data
2
C or the flash memory, after
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13. DTC