r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 515

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
21.3.3.2
Figure 21.14 shows an Operation Example during Data Transmission (4-Wire Bus Communication Mode, 8-Bit
SSU Data Transfer Length). During data transmission, the synchronous serial communication unit operates as
described below. (The data transfer length can be set from 8 to 16 bits using the SSBR register.)
When the MCU is set as the master device, it outputs a synchronous clock and data. When the MCU is set as a
slave device, it outputs data synchronized with the input clock while the SCS pin input is held low.
When the transmit data is written to the SITDR register after setting the TE_NAKIE bit in the SISR register to
1 (transmission enabled), the TDRE bit in the SISR register is automatically set to 0 (data is not transferred
from registers SITDR to SISDR) and the data is transferred from registers SITDR to SISDR. After that, the
TDRE bit is set to 1 (data is transferred from registers SITDR to SISDR) and transmission is started. If the TIE
bit in the SIER register is 1 at this time, a TXI interrupt request is generated.
After one frame of data is transferred while the TDRE bit is 0, the data is transferred from registers SITDR to
SISDR and the next frame transmission is started. If the 8th bit is transmitted while the TDRE bit is 1, the
TEND bit in the SISR register is set to 1 (the TDRE bit is 1 when the last bit of transmit data is transmitted) and
the state is retained. If the TEIE bit in the SIER register is 1 (transmit end interrupt request enabled) at this time,
a TEI interrupt request is generated. After transmission is completed, the SSCK pin is held high and the SCS
pin is set to high. To perform transmission continuously while the SCS pin is held low, write the next transmit
data to the SITDR register before transmitting the 8th bit.
Transmission cannot be performed while the ORER_AL bit in the SISR register is 1 (overrun error). Confirm
that the ORER_AL bit is 0 before transmission.
In contrast to clock synchronous communication mode, the SSO pin becomes high-impedance while the SCS
pin is in a high-impedance state in master device operation, and the SSI pin becomes high-impedance while the
SCS pin input is held high in slave device operation.
The sample flowchart is the same as that for clock synchronous communication mode (refer to Figure 21.8
Sample Flowchart for Data Transmission (Clock Synchronous Communication Mode)).
Preliminary document
Specifications in this document are tentative and subject to change.
Data Transmission
21. Clock Synchronous Serial Interface
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