r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 474

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 20.28
(1) When data does not match own station ID
(2) When data matches own station ID
20.3.4.3
U2SMR5 register
U2SMR5 register
U2SMR5 register
U2SMR5 register
This is the same function as in clock asynchronous serial I/O mode. Refer to 20.3.2.7 RXD2 Digital Filter
Select Function.
Bits b0 to b7 in
Bits b0 to b7 in
U2RB register
U2RB register
U2C1 register
U2C1 register
MPIE bit in
processing
processing
MPIE bit in
processing
processing
Serial data
Serial data
Hardware
Hardware
Software
Software
MP bit in
MP bit in
RI bit in
RI bit in
Preliminary document
Specifications in this document are tentative and subject to change.
Receive Operation Example during Multiprocessor Communication (with 8-Bit
Data/Multiprocessor Bit/One-Stop Bit)
RXD2 Digital Filter Select Function
1
1
(1) Detection of the MPRB bit
clears the MPIE bit to 0, and
requests a reception complete
interrupt.
Start
Start
(1) Detection of the MPRB bit
bit
bit
clears the MPIE bit to 0, and
requests a reception
complete interrupt.
D0
D0
Receive data (ID1)
Receive data (ID2)
D1
D1
ID1
(2) Read bits b0 to b7 in
One frame
One frame
the U2RB register.
D7
D7
(3) Reading bits b0 to b7 in
MPRB
MPRB
(2) Read bits b0 to b7 in
the U2RB register clears
the RI bit to 0.
the U2RB register.
Stop
Stop
bit
bit
(4) If data matches
(3) Reading bits b0 to b7 in
own station ID,
continue reception
without any setting
changes.
the U2RB register clears
the RI bit to 0.
D0
D0
Receive data (DATA1)
Receive data (DATA2)
D1
D1
(5) A reception
complete
interrupt is
requested.
One frame
One frame
ID2
(6) Read bits b0 to b7 in
the U2RB register.
ID1
(4) If data does not match own
station ID, set the MPIE bit
to 1 again.
(7) Reading bits b0 to b7 in
D7
D7
20. Serial Interface (UART2)
(5) No reception complete interrupt
the U2RB register clears
the RI bit to 0.
MPRB
MPRB
request is generated, and the
U2RB register retains state.
(8) Set the MPIE
DATA2
bit to 1 again.
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Idle state
Idle state