r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 442

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 20.3
(1) Transmit timing example (internal clock selected)
(2) Receive timing example (external clock selected)
The above diagram applies under the following conditions:
• CKDIR bit in U2MR register = 0 (internal clock)
• CRD bit in U2C0 register = 0 (CTS/RTS function enabled), CRS bit = 0 (CTS function selected)
• CKPOL bit in U2C0 register = 0 (transmit data is output at the falling edge and
• U2IRS bit in U2C1 register = 0 (interrupt request generation when the U2TB register is empty)
The above diagram applies under the following conditions:
• CKDIR bit in U2MR register = 1 (external clock)
• CRD bit in U2C0 register = 0 (CTS/RTS function enabled), CRS bit = 1
• CKPOL bit in U2C0 register = 0 (transmit data is output at the falling edge and
receive data is input at the rising edge of the transfer clock)
(RTS function selected)
receive data is input at the rising edge of the transfer clock)
fEXT: Frequency of external clock
U2RIC register
U2TIC register
Transfer clock
U2RB register
U2C1 register
U2C1 register
U2C0 register
U2C1 register
U2C1 register
U2C1 register
U2C1 register
TXEPT bit in
OER bit in
RE bit in
TE bit in
TE bit in
IR bit in
RI bit in
IR bit in
TI bit in
TI bit in
CTS2
TXD2
CLK2
RXD2
RTS2
CLK2
Preliminary document
Specifications in this document are tentative and subject to change.
Transmit and Receive Timing in Clock Synchronous Serial I/O Mode
Data is set in U2TB register
Data transfer from UART2 receive
register to U2RB register
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Dummy data is set in U2TB register
Data transfer from U2TB register to UART2 transmit register
TCLK
Set to 0 by acknowledgment of an interrupt request or by a program
Data transfer from U2TB register to UART2 transmit register
TC
1/fEXT
Set to 0 by acknowledgment of an interrupt request or by a program
Received data is acquired
Stops because high level is applied to CTS2
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5
Data read from U2RB register
Low level is applied when U2RB register is read
Make sure the following conditions are met when the
CLK2 pin input before receiving data is high:
• TE bit in U2C1 register = 1 (transmission enabled)
• RE bit in U2C1 register = 1 (reception enabled)
• Dummy data is written to U2TB register
D6
D7
TC = TCLK = 2 (n + 1) / fj
fj: Frequency of U2BRG count source
n: Value set in U2BRG register
Stops because TE bit is set to 0
D0 D1 D2 D3 D4 D5
(f1, f8, f32, or fC1)
D0 D1 D2 D3 D4 D5 D6 D7
20. Serial Interface (UART2)
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D6