r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 175

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 11.5
11.4.7
Address
m + 1
m - 4
m - 3
m - 2
m - 1
In the interrupt sequence, the FLG register and PC are saved on the stack.
After a total of 16 bits: higher 4 bits in the PC, higher 4 (IPL) and lower 8 bits in the FLG register, are saved on
the stack, the lower 16 bits in the PC are saved.
Figure 11.5 shows the Stack State Before and After Interrupt Request is Acknowledged.
Any other necessary registers should be saved at the beginning of the interrupt routine. The PUSHM instruction
can save all registers
Note:
m
MSB
Stack state before interrupt
1. Selected from registers R0, R1, R2, R3, A0, A1, SB, and FB.
Note:
request is acknowledged
Previous stack contents
Previous stack contents
Saving Registers
1. When an INT instruction for software interrupts numbered 32 to 63
has been executed, this SP is the SP specified by the U flag.
Otherwise it is ISP.
Preliminary document
Specifications in this document are tentative and subject to change.
Stack State Before and After Interrupt Request is Acknowledged
Stack
(1)
other than the SP with a single instruction.
LSB
[SP]
SP value before interrupt
request is acknowledged
(1)
Address
m + 1
m - 4
m - 3
m - 2
m - 1
m
MSB
Stack state after interrupt
request is acknowledged
Previous stack contents
Previous stack contents
FLGH
Stack
FLGL
PCM
PCL
PCL: Lower 8 bits of PC
PCM: 8 bits in the middle of PC
PCH: Higher 4 bits of PC
FLGL: Lower 8 bits of FLG
FLGH: Higher 4 bits of FLG
PCH
LSB
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[SP]
New SP value
11. Interrupts
(1)