r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 259

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
15.3.3
Note:
Table 15.4
Table 15.5
Pulse output mode
Event counter mode
Pulse width measurement mode
Pulse period measurement mode 0: Measure from one rising edge to the next rising edge
All modes
TEDGSEL Bit (I/O polarity switch bit)
After Reset
1. Set the TOPCR bit after other SFR settings are completed.
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 00113h (TRJIOC_0)
The TEDGSEL bit is used to switch the TRJO output polarity and the TRJIO I/O edge and polarity. In pulse
output mode, only the inversion/non-inversion of toggle flip-flop is controlled. The toggle flip-flop is initialized
when the TRJMR register is written or 1 is written to the TSTOP bit in the TRJCR register.
Symbol TIOGT1
TEDGSEL I/O polarity switch bit
Operating Mode
Operating Mode
TIOSEL
TIOGT0
TIOGT1
TOPCR
Bit
Symbol
TOENA
TIPF0
TIPF1
Timer RJ I/O Control Register (TRJIOC)
Preliminary document
Specifications in this document are tentative and subject to change.
TRJIO I/O Edge and Polarity Switching
TRJO Output Polarity Switching
b7
0
TRJIO output control bit
TRJO output enable bit
Event input select bit
TRJIO input filter select bits
TRJIO count control bits
TIOGT0
b6
0
Bit Name
1: Output is started at low
0: Count at rising edge
1: Count at falling edge
1: High-level width is measured
1: Measure from one falling edge to the next falling edge
1: Output is started at high
0: Output is started at high
0: Low-level width is measured
0: Output is started at low
TIPF1
b5
0
(1)
TIPF0
b4
Function varies depending on the operating mode (refer
0
to Tables 15.4 and 15.5).
0: TRJIO output enabled (toggle output is started)
1: TRJIO output disabled (toggle output is stopped)
0: TRJO output disabled (port)
1: TRJO output enabled
0: Input from TRJIO pin
1: Input from hardware LIN
b5 b4
b7 b6
0 0: No filter
0 1: Filter enabled, sampling at f1
1 0: Filter enabled, sampling at f8
1 1: Filter enabled, sampling at f32
0 0: Event is counted
0 1: Event is counted only during INT1 high period
1 0: Event is counted during timer RC output signal
1 1: Do not set.
period specified by RCCPSEL bit in TRJISR
register
TIOSEL
b3
0
Function
Function
TOENA
b2
0
Function
TOPCR TEDGSEL
b1
0
b0
0
Page 228 of 725
15. Timer RJ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W