r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 725

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
29.4.5
(a) The contents of the interrupt control register can be rewritten only while no interrupt requests
(b) When rewriting the contents of the interrupt control register after disabling the interrupt, be careful to
(c) When using the I flag to disable an interrupt, set the I flag as shown in the sample programs below. (Refer
Examples 1 to 3 show how to prevent the I flag from being set to 1 (interrupt enabled) before the contents of the
interrupt control register are rewritten due to effects of the internal bus and the instruction queue buffer.
Example 1: Use the NOP instructions to pause the program until the interrupt control register is
rewritten
Example 2: Use a dummy read to delay the FSET instruction
Example 3: Use the POPC instruction to change the I flag
corresponding to that register are generated. If an interrupt request may be generated, disable the interrupt
before rewriting the contents of the interrupt control register.
choose appropriate instructions
Changing any bit other than the IR bit
If an interrupt request corresponding to the register is generated while executing the instruction, the IR bit
may not be set to 1 (interrupt requested), and the interrupt may be ignored. If this causes a problem, use
one of the following instructions to rewrite the contents of the register:
Applicable instructions....... AND, OR, BCLR, and BSET
Changing the IR bit
Depending on the instruction used, the IR bit may not be set to 0 (no interrupt requested). Use the MOV
instruction to set the IR bit to 0.
to (b) regarding rewriting the contents of interrupt control registers using the sample programs.)
INT_SWITCH1:
INT_SWITCH2:
INT_SWITCH3:
Rewriting Interrupt Control Register
FCLR
AND.B
NOP
NOP
FSET
FCLR
AND.B
MOV.W
FSET
PUSHC
FCLR
AND.B
POPC
Preliminary document
Specifications in this document are tentative and subject to change.
I
#00H, 0056H
I
I
#00H, 0056H
MEM, R0
I
I
#00H, 0056H
FLG
FLG
; Interrupt disabled
; Set the TRJIC_0 register to 00h
;
; Interrupt enabled
; Interrupt disabled
; Set the TRJIC_0 register to 00h
; Dummy read
; Interrupt enabled
; Interrupt disabled
; Set the TRJIC_0 register to 00h
; Interrupt enabled
29. Usage Notes
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