r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 411

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
19.3
19.3.1
Table 19.4
Notes:
Transfer data format
Transfer clock
Transmit start conditions
Receive start conditions
Interrupt request
generation timing
Error detection
Selectable functions
UART0 supports two modes: clock synchronous serial I/O mode and clock asynchronous serial I/O (UART) mode.
1. When an external clock is selected, the requirements must be met in either of the following states:
2. If an overrun error occurs, the receive data (b0 to b7) in the U0RB register is undefined. The U0RIF bit in the
In clock synchronous serial I/O mode, transmission or reception is performed using a transfer clock.
Table 19.4 lists the Clock Synchronous Serial I/O Mode Specifications and Table 19.5 lists the Registers and
Settings Used in Clock Synchronous Serial I/O Mode.
• The external clock is set to high when the CKPOL bit in the U0C0 register is 0 (transmit data is output at the
• The external clock is set to low when the CKPOL bit is 1 (transmit data is output at the rising edge and receive
U0IR register remains unchanged.
falling edge and receive data is input at the rising edge of the transfer clock).
data is input at the falling edge of the transfer clock).
Operation
Item
Clock Synchronous Serial I/O Mode
Preliminary document
Specifications in this document are tentative and subject to change.
Clock Synchronous Serial I/O Mode Specifications
Transfer data length: 8 bits
• The CKDIR bit in the U0MR register is 0 (internal clock): fi/(2 (n + 1))
• The CKDIR bit in the U0MR register is 1 (external clock): fEXT (input from the CLK pin)
To start transmission, the following requirements must be met:
• The TE bit in the U0C1 register is set to 1 (transmission enabled).
• The TI bit in the U0C1 register is set to 0 (data present in the U0TB register).
To start reception, the following requirements must be met:
• The RE bit in the U0C1 register is set to 1 (reception enabled).
• The TE bit in the U0C1 register is set to 1 (transmission enabled).
• The TI bit in the U0C1 register is set to 0 (data present in the U0TB register).
For transmission, one of the following can be selected.
For reception
Overrun error
• CLK polarity selection
• LSB first or MSB first selection
• Continuous receive mode selection
fi = f1, f8, f32, or fC1
n = Value set in the U0BRG register (00h to FFh)
- The U0IRS bit in the U0C1 register is set to 0 (transmit buffer empty):
- The U0IRS bit in the U0C1 register is set to 1 (transmission completed):
When data is transferred from the UART0 receive register to the U0RB register (at
completion of reception).
This error occurs if the next data reception is started and the 7th bit is received before
the U0RB register is read.
The output and input timing of transfer data can be selected to be either the rising or the
falling edge of the transfer clock.
The start bit can be selected to be bit 0 or bit 7 when transmission and reception are
started.
Reading the U0RB register enables reception at the same time.
When data is transferred from the U0TB register to the UART0 transmit register (at
start of transmission).
When data transmission from the UART0 transmit register is completed.
(2)
Specification
(1)
19. Serial Interface (UART0)
(1)
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